Coding device and communication system using the same

• US 20050246609A1
• Filed: 07/11/2005
• Published: 11/03/2005
• Est. Priority Date: 07/10/1998
• Status: Abandoned Application

• Current Assignee: Timothy J. Moulsley
• Original Assignee: Timothy J. Moulsley
• Inventors: Moulsley, Timothy J.
• Application Number:
  US11/178,732
• Publication Number:
  US 20050246609A1
• Time in Patent Office: Days
• US Class Current: 714/752
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/23 using convolutional codes, e.g. unit memory codes
• CPC Class Codes: H03M 13/2707 Simple row-column interleaver, i.e. pure block interleaving
• CPC Class Codes: H03M 13/2714 Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS], e.g. as defined in technical specification TS 25.212
• CPC Class Codes: H03M 13/2792 Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/635 Error control coding in combination with rate matching
• CPC Class Codes: H03M 13/6356 by repetition or insertion of dummy data, i.e. rate reduction
• CPC Class Codes: H03M 13/6362 by puncturing
• CPC Class Codes: H03M 13/6508 Flexibility, adaptability, parametrability and configurability of the implementation
• CPC Class Codes: H03M 13/6516 Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
• CPC Class Codes: H03M 13/6558 3GPP2
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 1/0069 Puncturing patterns
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/08 by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence

Abstract

A coding device includes a coding circuit for converting a digital input into a coded output having a greater number of bits than the input, an interleaving circuit for combining a plurality of words of the coded output and producing therefrom a data block having a plurality of the interleaved words, and a puncturing circuit or repeating circuit for puncturing or repeating bits from the data block. The puncturing or repeating circuit uses a deleting or repeating pattern to provide data words for transmission during respective frames of a transmission channel. The deleting or repeating pattern is selected depending upon the characteristics of the coding circuit and of the interleaving circuit. The coding device is for use in a cordless communication system.

Claims

1-10. -10. (canceled)

11. A communication system comprising a transmitter and a receiver, the transmitter comprising a digital input, a coding device for generating data bits for transmission, and means for transmitting the data bits during respective frames of a transmission channel, the coding device comprising a coding circuit for generating a coded output having a greater number of bits than the digital input, an interleaving circuit for operating on the coded output to generate a data block comprising a plurality of interleaved words, and a rate matching circuit for adjusting the number of bits in the data block, the rate matching circuit having means for adjusting the number of bits in the data block using a rate matching pattern to provide data bits, and means for selecting the rate matching pattern depending on an associated bit deletion or repetition pattern that is selected to ensure that the deleted or repeated bits of the data block are not required to enable all bits from the digital input to be reconstructed, and the receiver comprising means for receiving the data bits and a data reconstruction circuit having means for adjusting the number of bits in the data block to reverse the action of the rate matching circuit, thereby reconstructing the interleaved words, a de-interleaving circuit having means for generating each of the plurality of interleaved words, and a channel decoder, the data reconstruction circuit having means for selecting the rate matching pattern depending on the characteristics of the coding device.

12. A system as claimed in claim 11, wherein said means for selecting select the rate matching pattern in such a way that all bits of the digital input can be derived from bits in the data block other than the deleted or repeated bits of the data block.

13. A system as claimed in claim 11, wherein the rate matching pattern for each interleaved word within the data block is offset with respect to the rate matching pattern of an adjacent interleaved word or words within the data block.

14. A system as claimed in claim 11, wherein said means for selecting select the rate matching pattern as a function of an interleaving depth of the interleaving circuit.

15. A system as claimed in claim 11, wherein the coding circuit applies convolutional coding and said means for selecting select the rate matching pattern as a function of a constraint length of the convolutional code.

16. A system as claimed in claim 11, wherein the transmitter comprises additional coding devices, each for coding a respective digital input, and a multiplexer for combining output data words of said coding device and said additional coding devices for subsequent transmission by the transmission means on a single transmission channel.

17. A system as claimed in claim 16, wherein the outputs of said coding device and said additional coding devices are selected to have different data rates, the combined data rate corresponding to the channel capacity of the transmission channel.

18. A system as claimed in claim 11, wherein the rate matching pattern forms a matrix including change bits that indicate a change of corresponding bits of said interleaved words within said data block, wherein each row of said matrix includes a maximum of one of said change bits.

19. A system as claimed in claim 11, wherein said coding circuit has one of:

(a) a fixed code rate and (b) a predetermined number of rates for a variable data source.

20. A system as claimed in claim 11, wherein said interleaving circuit is not adaptive.

21. A system as claimed in claim 11, wherein said interleaving circuit has a constant input bit rate.

22. A system as claimed in claim 11, wherein said coding circuit has one of:

(a) a fixed code rate and (b) a predetermined number of rates for a variable data source, and wherein said interleaving circuit is not adaptive.

23. A system as claimed in claim 11, wherein said rate matching circuit alters a coding rate of said coding circuit according to the bit deletion or repetition pattern.

25. A system as claimed in claim 11, wherein said rate matching pattern includes change bits for deleting or repeating bits of said data block and said change bits are offset with respect to each other along adjacent columns of a matrix of said rate matching pattern.

24. A method of operating a communication system comprising a transmitter and a receiver, the method comprising the transmitter operating on the digital input to generate a coded output having a greater number of bits than the digital input, operating on the coded output to generate a data block comprising a plurality of interleaved words and adjusting the number of bits in the data block using a rate matching pattern to provide data bits for transmission during respective frames of a transmission channel, and the receiver receiving the data bits, adjusting the number of bits in the data block to reverse the action of the rate matching operation, thereby reconstructing the interleaved words, and de-interleaving and decoding the interleaved words to reverse the actions of the interleaving and coding operations, wherein the rate matching pattern is selected depending on an associated bit deletion or repetition pattern that is selected to ensure that the deleted or repeated bits are not required to enable all bits from the digital input to be reconstructed.

26. The method of claim 24, wherein said rate matching pattern includes change bits for deleting or repeating bits of said data block and said change bits are offset with respect to each other along adjacent columns of a matrix of said rate matching pattern.