Semiconductor device
First Claim
1. A semiconductor device comprising:
- a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions;
a surface source electrode connected to the source region of each of the cells and provided on the first surface;
a strap member coupled with the surface source electrode by ultrasonic waves;
a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof;
a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface; and
a drain electrode provided on the second surface and shared by the cells.
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Abstract
A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.
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Citations
2 Claims
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1. A semiconductor device comprising:
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a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions;
a surface source electrode connected to the source region of each of the cells and provided on the first surface;
a strap member coupled with the surface source electrode by ultrasonic waves;
a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof;
a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface; and
a drain electrode provided on the second surface and shared by the cells.
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2-7. -7. (canceled)
Specification