Sub-micron high input voltage tolerant input output (I/O) circuit

• US 20050248892A1
• Filed: 07/14/2005
• Published: 11/10/2005
• Est. Priority Date: 01/09/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Janardhanan S. Ajit
• Inventors: Ajit, Janardhanan S.
• Granted Patent: US 7,292,072 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Claims

1. An apparatus for generating a first bias voltage, the apparatus comprising:

a first input for accepting a pad voltage;

an second input for accepting a second bias voltage, the second input having a corresponding output, the second bias voltage having a first voltage level when the corresponding output is enabled and having a second voltage level when the corresponding output is disabled; and

a circuit for providing the first voltage level of the second bias voltage as the first bias voltage when the pad voltage is less the second voltage level of the second bias voltage and for providing the pad voltage as the first bias voltage otherwise,

wherein the second voltage level of the second bias voltage is greater than the first voltage level of the second bias voltage.

2. The apparatus of claim 1, wherein the second voltage level is about 3.3 Volts and the first voltage level is about 1.2 Volts.

3. The apparatus of claim 1, further comprising an N-channel Metal Oxide Semiconductor (NMOS) for providing the second input and the corresponding output and a P-channel Metal Oxide Semiconductor (PMOS) for providing the first input.

4. The apparatus of claim 3, wherein the first bias voltage is generated between the NMOS and the PMOS.

5. The apparatus of claim 3, wherein the second voltage level minus an offset voltage level is at a gate of the PMOS.

6. The apparatus of claim 5, wherein the offset voltage level is equal to a threshold voltage of a transistor.

7. The apparatus of claim 3, wherein the second voltage level is at a gate of the NMOS.

8. A method for generating a bias voltage at a bias node using a bias circuit, the method comprising:

accepting a pad voltage from an input/output circuit node;

accepting a power supply voltage;

accepting an intermediate voltage;

providing a voltage derived from the power supply voltage or the intermediate voltage to the bias node when the power supply voltage is greater than a first predetermined value or the intermediate voltage is greater than a second predetermined value; and

providing a voltage derived from the pad voltage to the bias node when the power supply voltage is not greater than the first predetermined value and the intermediate voltage is not greater than the second predetermined value.

9. The method of claim 8, further comprising providing a voltage derived from the power supply voltage and the intermediate voltage to the bias node when the power supply voltage is greater than the first predetermined value and the intermediate voltage is greater than the second predetermined value.

10. A method for generating a bias voltage at a bias node using a bias circuit, the method comprising:

accepting a pad voltage from an input/output circuit node;

accepting a power supply voltage;

providing a voltage derived from the power supply voltage to bias node when the power supply voltage is greater than a predetermined value; and

providing a voltage derived from the pad voltage to the bias node when the power supply voltage is not greater than the predetermined value.

11. The method of claim 10, wherein the predetermined value is about 3.3 Volts.

12. The method of claim 10, wherein the power supply voltage is accepted by a P-channel Metal Oxide Semiconductor (PMOS).

13. The method of claim 10, wherein the pad voltage is accepted by an N-channel Metal Oxide Semiconductor (NMOS).

14. The method of claim 10, wherein the power supply voltage is accepted by a P-channel Metal Oxide Semiconductor (PMOS) and wherein the pad voltage is accepted by an N-channel Metal Oxide Semiconductor (NMOS).

15. The method of claim 14, wherein the PMOS and the NMOS are connected at the bias node.

16. An apparatus for generating a bias voltage at a bias node, the apparatus comprising:

a first input for accepting a pad voltage from an input/output circuit;

a second input for accepting an output enable signal;

a third input for accepting a first input voltage; and

an output circuit for providing the first input voltage to the bias node when the output enable signal is at an enable value and for providing a voltage depending on the pad voltage to the bias node when the output enable signal is at a disable value.

17. The apparatus of claim 16, further comprising:

a fourth input for accepting a second input voltage,

wherein the output circuit provides a constant voltage equal to the first input voltage to the bias node until the pad voltage is equal to the first input voltage and provides an increasing voltage tracking the pad voltage when the pad voltage is not less than the first input voltage but is less than the second input voltage minus an offset voltage.

18. The apparatus of claim 17, wherein the offset voltage is equal to a threshold voltage of a transistor.

19. The apparatus of claim 17, wherein the offset voltage is equal to a threshold voltage of a P-channel Metal Oxide Semiconductor (PMOS).

20. The apparatus of claim 17, wherein the offset voltage is equal to a threshold voltage of an N-channel Metal Oxide Semiconductor (NMOS).