Memory system for network broadcasting applications and method for operating the same

• US 20050248994A1
• Filed: 05/19/2005
• Published: 11/10/2005
• Est. Priority Date: 11/19/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Benedix, Alexander, Duregger, Reinhard, Ruf, Wolfgang, Dankowski, Stefan
• Granted Patent: US 7,305,525 B2
• Time in Patent Office: Days
• US Class Current: 365/189.50
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: H04N 21/2182 involving memory arrays, e.g. RAID disk arrays RAID arrays per se G06F3/0689; use of parity to protect data in RAID systems G06F11/1008
• CPC Class Codes: H04N 21/23116 involving data replication, e.g. over plural servers synchronization of replicated data G06F11/1658; error detection or correction by means of data replication G06F11/2053; replication in distributed file systems G06F16/10; replication in distributed file systems G06F16/27; replication or mirroring of data in data networks H04L67/1095
• CPC Class Codes: H04N 21/2312 Data placement on disk arrays data placement in general G06F3/0604
• CPC Class Codes: H04N 21/2323 using file mapping

Abstract

A memory system for network broadcasting applications, such as video/audio applications, has at least one memory which is divided into a plurality of addressable memory units, which have a respective dedicated output for interchanging data. The inputs of a matrix switch are connected to a respective output of a different memory unit. The matrix switch is operated such that a plurality of the memory units are connected to its output in a sequential order. A first sequence of memory units and a second sequence of memory units are connected to its output independently. This results in a memory system, which can handle a number of requests to the same memory at staggered times. The interaction of the individual memory units with the matrix switch allows a high data throughput and a short access time.

Claims

1. A memory system for network broadcasting applications, comprising:

at least one memory divided into a plurality of addressable memory units each including a dedicated output for interchanging data; and

a matrix switch including inputs, at least one output, and at least one control input, the inputs of the matrix switch being connectable to the at least one output of the matrix switch, wherein;

the inputs of the matrix switch are connected to a respective output of a different memory unit;

the control input of the matrix switch sets which of the inputs of the matrix switch is connected to the output of the matrix switch;

the plurality of the addressable memory units are connectable to the output of the matrix switch in a sequential order, a first sequence of memory units and a second sequence of memory units being connected to the output of the matrix switch independently; and

the memory units are capable of continuing to output data records even if the sequential order is interrupted.

2. The memory system as claimed in claim 1, wherein the memory units store respective data records, the memory units together forming a cohesive data record for an application.

3. The memory system of claim 2, wherein the application is a video/audio application.

4. The memory system as claimed in claim 1, wherein the output of the matrix switch has at least two different users connected thereto, the user accessing the memory independently.

5. The memory system as claimed in claim 1, wherein the memory is actuated such that data stored in a respective memory unit are applied sequentially to the output of the memory unit.

6. The memory system as claimed in claim 1, wherein the size of the memory units is adjusted dynamically.

7. The memory system as claimed in claim 1, wherein the memory system has a further memory with a data access time slower than a data access time for the at least one memory, and the memories each being connected to respective users independently.

8. The memory system as claimed in claim 7, wherein the at least one memory is an SRAM, DRAM, MRAM or Flash memory, and the further memory is a hard disk memory.

9. The memory system as claimed in claim 7, wherein the at least one memory stores a data record for a first application, and

the further memory stores a data record for a second application, with an earlier date of origin than the first application.

10. The memory system as claimed in claim 9, wherein the first application is a video/audio application.

11. The memory system as claimed in claim 9, wherein the second application is a video/audio application.

12. A method for operating a memory system as claimed in claim 1, wherein

each memory unit stores a data record,

a respective different memory unit from the memory units is addressed in respective sequential order for at least two sequences to be output, and

the data records are applied to the output in a respective sequence via the matrix switch.

13. The method as claimed in claim 12, wherein one of the memory units is addressed for each sequence to be output, and

for each sequence to be output, starting at the addressed memory unit, a respective complete data record from this and from subsequently sequentially addressed memory units is applied to the output of the matrix switch.

14. The method as claimed in claim 12, wherein data stored in a respective memory unit are applied sequentially to the output of the memory unit in question.