Biosensor performance enhancement features and designs

• US 20050250272A1
• Filed: 05/03/2005
• Published: 11/10/2005
• Est. Priority Date: 05/03/2004
• Status: Abandoned Application

• Current Assignee: University of Hawai'i
• Original Assignee: University of Hawai'i
• Inventors: Holm-Kennedy, James W.
• Application Number:
  US11/120,649
• Publication Number:
  US 20050250272A1
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

Isolation of semiconductor based biosensors is described. The present invention is directed to prevention of undesirable influences including, but not limited to, chip leakage current. Several forms of sensor isolation and other protective means affect protection from adverse chip influences. The effect of biochemical attachment outside the sensor active region may have adverse effects on sensor performance. This potential problem is averted using protective design features.

Claims

1. A biosensor performance enhancement comprising:

providing a P substrate,

providing an N region,

providing an oxide or insulation layer between the P substrate and N region,

attaching a source and a drain between a conducting channel on the N region at an attachment region,

providing isolation devices surrounding the attachment region.

2. The method of claim 1, wherein the oxide or insulation layer is thick.

3. The method of claim 2, wherein providing the thick oxide or insulation layer comprises creating a difference between substrate voltage and overlying drain and/or source conduit voltage such that an inversion layer and pseudo PN junction are formed.

4. The method of claim 2, further comprising providing a reverse bias isolation.

5. The method of claim 1, wherein the isolation devices create P wells for isolating the sensor from the substrate.

6. The method of claim 5, further comprising placing an epitaxal N layer on the P substrate.

7. The method of claim 5, wherein a back bias exists between the P substrate and the attachment region of the epitaxal N layer.

8. The method of claim 1, further comprising creating trench isolation.

9. The method of claim 8, wherein the creating trench isolation further comprises surrounding a sensor and abutting a sensor with a trench cut deep into the P substrate.

10. The method of claim 9, wherein maintaining minimum sensor, channel source and drain inversionable areas reduces induced junction leakage.

11. The method of claim 1, further comprising etching a mesa around the sensor for creating mesa isolation.

12. The method of claim 1, further comprising attaching biochemical charges to the substrate for inducing a junction leakage current.

13. The method of claim 1, further comprising providing a sensor region fabricated on a semiconductor substrate and providing a conduction region protected by insulators and added to the remainder of the semiconductor substrate region.

14. The apparatus of claim 13, wherein a conductive layer has a pre-selected bias applied with respect to the back gate bias.

15. A biosensor performance apparatus comprising:

a P substrate,

an N region,

an oxide or insulation layer between the P substrate and N region,

a source and a drain between a conducting channel on the N region on an attachment region,

one or more isolation devices surrounding the attachment region.

16. The apparatus of claim 15, wherein the oxide or insulation layer is thick, and wherein the thick oxide or insulation layer creates a difference between substrate voltage and overlying drain and/or source conduit voltage such that an inversion layer and pseudo PN junction are formed.

17. The apparatus of claim 15, wherein the one or more isolation devices are P wells for isolating the sensor from the substrate, and further comprising an epitaxal N layer on the P substrate.

18. The apparatus of claim 15, wherein the isolation devices are trench isolation, and wherein the trench isolation further comprises a trench cut deep into the P substrate surrounding and abutting a sensor.

19. The apparatus of claim 15, wherein the isolation devices are mesa isolation, and wherein a mesa is etched around the sensor.

20. The apparatus of claim 15, further comprising a sensor region fabricated on a semiconductor substrate and a conduction region protected by insulators and added to the remainder of the semiconductor substrate region.