Non-volatile memory cells having floating gate and method of forming the same

• US 20050250283A1
• Filed: 07/18/2005
• Published: 11/10/2005
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Sung-Chul Park
• Original Assignee: Sung-Chul Park
• Inventors: Park, Sung-Chul
• Granted Patent: US 7,338,859 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory cell having a floating gate and a method of forming the same. The non-volatile memory cell includes a device isolation layer that is formed in a semiconductor substrate and defines an active region. A floating gate is disposed over the active region and is comprised of a plurality of first conductive patterns and a plurality of second conductive patterns that are alternately stacked. A first insulation layer is disposed between the floating gate and the active region. One of the first conductive pattern and the second conductive pattern protrudes to form concave and convex sidewalls of the floating gate. Therefore, a surface area of the floating gate increases, thereby raising coupling ratio between the floating gate and the control gate electrode. As a result, an operating voltage of the non-volatile memory cell can be reduced.

Claims

1-8. -8. (canceled)

9. A method of forming a non-volatile memory cell comprising:

forming a device isolation layer in a semiconductor substrate to define an active region;

forming a first insulation layer over the active region;

forming a gate conductive layer over an entire surface of the semiconductor substrate with the first insulation layer, wherein the gate conductive layer comprises a plurality of first conductive layers and second conductive layers that are alternately stacked; and

forming a floating gate with concave and convex sidewalls by applying a patterning process including an isotropic etching of the gate conductive layer,

wherein the isotropic etching has etch selectivity with respect to the first and second conductive layers.

10. The method of claim 9, wherein one of the first and second conductive layers is formed of a doped polysilicon layer, and the other of the first and second conductive layers is formed of a doped silicon germanium layer.

11. The method of claim 10, wherein the isotropic etching is performed by dry etching using etch gas that includes HeO₂,

wherein the etch gas etches the doped silicon germanium layer faster than the doped polysilicon layer.

12. The method of claim 10, wherein the doped polysilicon layer and the doped silicon germanium layer are doped using an in-situ method.

13. The method of claim 9, further comprising a step of forming a gate interlayer dielectric pattern and a control gate electrode over the floating gate,

wherein the gate interlayer dielectric pattern and the control gate electrode are formed on a top surface and on the concave and convex sidewalls of the floating gate.

14. The method of claim 13, wherein the step of forming the floating gate, the gate interlayer dielectric pattern, and the control gate electrode comprises:

forming a preliminary gate conductive pattern by patterning the gate conductive layer using an anisotropic etching;

forming a gate conductive pattern having concave and convex sidewalls by etching the sidewalls of the preliminary gate conductive pattern using an isotropic etching process;

sequentially forming a gate interlayer dielectric layer and a control gate conductive layer on an entire surface of the semiconductor substrate with the gate conductive pattern; and

successively patterning the control gate conductive layer, the gate interlayer dielectric layer and the gate conductive pattern to form a floating gate, a gate interlayer dielectric pattern and a control gate electrode that are sequentially stacked, wherein the control gate electrode crosses over the active region.

15. The method of claim 14, further comprising a step of forming an impurity diffusion layer in the active region at both sides of the control gate electrode after forming the control gate electrode.

16. The method of claim 13, further comprising a step of forming a selection gate pattern that crosses over the active region at one side of the control gate electrode.

17. The method of claim 16, wherein the steps of forming the floating gate, the gate interlayer dielectric pattern, the control gate electrode, and a selection gate pattern, comprise:

forming a preliminary gate conductive pattern by patterning the gate conductive layer using anisotropic etching;

forming a gate conductive pattern by isotropically etching sidewalls of the preliminary gate conductive pattern;

forming a control gate dielectric layer and a control gate conductive layer on an entire surface of the substrate with the gate conductive pattern; and

successively patterning the control gate conductive layer, the gate interlayer dielectric layer and the gate conducive pattern to form a floating gate, a gate interlayer dielectric pattern and a control gate electrode that are sequentially stacked, and simultaneously to form a selection gate pattern crossing over the active region at one side of the control gate electrode.

18. The method of claim 16, further comprising a step of forming a floating impurity diffusion layer in a predetermined region of the active region before forming the first insulation layer,

wherein the floating gate and the selection gate pattern are formed at both sides of the floating impurity diffusion layer, and

wherein a portion of the floating gate overlaps a portion of the floating impurity diffusion layer.

19. The method of claim 18, after forming the first insulation layer and before forming the gate conductive layer, further comprising:

patterning the first insulation layer to expose a predetermined region of the floating impurity diffusion layer; and

forming a second insulation layer over the exposed floating impurity diffusion layer,

wherein the second insulation layer is formed thinner than the first insulation layer, and

wherein the second insulation layer is disposed in the overlapping region of the floating gate and the floating impurity diffusion layer.

20-24. -24. (canceled)

25. A method of forming a non-volatile memory cell comprising:

forming an active region in a semiconductor substrate; and

forming a floating gate having sidewalls over the active region, the sidewalls having protruding portions.

26. The method of claim 25, wherein the step of forming a floating gate comprises forming a plurality of first conductive patterns and a plurality of second conductive patterns.

27. The method of claim 26, wherein one of the plurality of first conductive patterns and the plurality of second conductive patterns forms the protruding portions of the sidewalls of the floating gate.

28. The method of claim 27, wherein the one of the plurality of first conductive patterns and the plurality of second conductive patterns comprise doped polysilicon layers and the other of the plurality of first conductive patterns and the plurality of second conductive patterns comprise doped silicon germanium layers.