Thin films and methods of making them

• US 20050250302A1
• Filed: 07/12/2005
• Published: 11/10/2005
• Est. Priority Date: 02/12/2001
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM America Incorporated (ASM International NV)
• Inventors: Raaijmakers, Ivo, Todd, Michael A.
• Granted Patent: US 7,285,500 B2
• Time in Patent Office: Days
• US Class Current: 438/607
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C23C 16/0272 Deposition of sub-layers, e.g. to promote the adhesion of the main coating
• CPC Class Codes: C23C 16/22 characterised by the deposition of inorganic material, other than metallic material
• CPC Class Codes: C23C 16/24 Deposition of silicon only
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/308 Oxynitrides
• CPC Class Codes: C23C 16/325 Silicon carbide
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/36 Carbonitrides
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02529 : Silicon carbide
• CPC Class Codes: H01L 21/02532 : Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 : N-type
• CPC Class Codes: H01L 21/02579 : P-type
• CPC Class Codes: H01L 21/02592 : amorphous
• CPC Class Codes: H01L 21/02595 : polycrystalline
• CPC Class Codes: H01L 21/02598 : monocrystalline
• CPC Class Codes: H01L 21/0262 : Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02667 : Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/2257 : the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28035 : the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28044 : the conductor comprising at least another non-silicon conductive layer
• CPC Class Codes: H01L 21/28194 : by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28525 : the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 21/28556 : by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/3185 : of siliconnitrides
• CPC Class Codes: H01L 21/32055 : Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 28/84 : being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 29/127 : Quantum box structures
• CPC Class Codes: H01L 29/51 : Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66181 : Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/66242 : Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 31/1804 : comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/182 : Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
• CPC Class Codes: H01L 31/202 : including only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/546 : Polycrystalline silicon PV cells
• CPC Class Codes: Y02E 10/547 : Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 438/933 : Germanium or silicon or Ge-Si on III-V

Abstract

Thin, smooth silicon-containing films are prepared by deposition methods that utilize a silicon containing precursor. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 Å or less, a surface roughness of about 5 Å rms or less, and a thickness non-uniformity of about 20% or less. Preferred silicon-containing films display a high degree of compositional uniformity when doped or alloyed with other elements. Preferred deposition methods provide improved manufacturing efficiency and can be used to make various useful structures such as wetting layers, HSG silicon, quantum dots, dielectric layers, anti-reflective coatings (ARC'"'"'s), gate electrodes and diffusion sources.

Claims

1. A method of increasing semiconductor manufacturing device yield, comprising:

identifying a semiconductor device manufacturing process that comprises depositing a Si-containing film onto a substrate using silane to produce a number N_T of semiconductor devices, of which a number N_A of the devices are acceptable and a number N_U of the devices are unacceptable;

wherein the Si-containing film has an average thickness of about 2000 Å

or less;

wherein the substrate has a surface area of about 300 cm² or greater; and

wherein the process has a device yield equal to N_A/N_T; and

replacing the silane with trisilane in the semiconductor device manufacturing process to increase the device yield.

2. The method of claim 1, wherein the semiconductor device manufacturing process comprises thermal CVD of silane at a temperature T_s, further comprising depositing the trisilane by thermal CVD at a temperature T_t, where T_s>

T_t.

3. The method of claim 2, wherein T_t is in the range of about 450°

C. to about 600°

C.

4. The method of claim 2, wherein T_t is in the range of about 450°

C. to about 525°

C.

5. The method of claim 1, wherein the semiconductor device manufacturing process comprises introducing trisilane to a chamber, further comprising using a bubbler to introduce the trisilane to the chamber.

6. The method of claim 5, wherein the bubbler is temperature-regulated.

7. The method of claim 1, wherein the Si-containing film has an average thickness of about 300 Å

or less.

8. The method of claim 1, wherein the Si-containing film has an average thickness of about 150 Å

or less.

9. The method of claim 1, wherein the substrate has a surface area of about 700 cm² or greater.

10. The method of claim 1, wherein the device yield is increased by about 2% or more.

11. The method of claim 1, wherein the device yield is increased by about 5% or more.

12. An integrated circuit comprising a continuous amorphous Si-containing film having a thickness that is 15 Å

or greater and that is 150 Å

or less, a surface area of about one square micron or greater, and a thickness non-uniformity of about 10% or less for a mean film thickness in the range of 100 Å

to 150 Å

, a thickness non-uniformity of about 15% or less for a mean film thickness in the range of 50 Å

to 99 Å

, and a thickness non-uniformity of about 20% or less for a mean film thickness of less than 50 Å

.

13. The integrated circuit of claim 12, further comprising a dielectric material having a surface in contact with the Si-containing film, wherein the surface in contact has an area of about 0.5 square micron or greater.

14. The integrated circuit of claim 12, wherein the Si-containing film further comprises a dopant element selected from the group consisting of boron, arsenic, and phosphorous.

15. The integrated circuit of claim 14, wherein the dopant element is uniformly distributed throughout the Si-containing film.

16-61. -61. (canceled)