Method for completing full cacheline stores with address-only bus operations

• US 20050251623A1
• Filed: 04/15/2004
• Published: 11/10/2005
• Est. Priority Date: 04/15/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Williams, Derek Edward, Arimilli, Ravi Kumar, Guthrie, Guy Lynn, Shen, Hugh
• Granted Patent: US 7,360,021 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811

Abstract

A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.

Claims

1. In a data processing system having multiple processors each having a processor core, store queue (STQ) mechanism, RC mechanism, and associated processor cache, a method for facilitating cache line updates responsive to processor-issued store operations, said method comprising:

determining when a store queue entry selected for dispatch by an RC machine provides an update to an entire cache line; and

completing said update to said entire cache line with address-only operations, wherein no data tenure is requested when an entire cache line is being overwritten.

2. The method of claim 1, wherein said determining step comprises:

tracking processor issued store operations gathered to said store queue entry via byte enable bits, wherein each storage granule within said store queue entry is provided a corresponding byte enable bit that is set when the storage granule is updated by a store operation;

logically ANDing each of the byte enable bits of the store queue entry to determining when all storage granules of said store queue entry have been updated; and

providing a full signal to the STQ controller when said logically ANDing step indicates all storage granules of said entry have been updated.

3. The method of claim 2, wherein said store queue mechanism includes a STQ controller, said method further comprising:

tagging said entry as eligible for dispatch when said full signal is received at said STQ controller; and

enabling selection of said entry by arbitration logic of said STQ controller.

4. The method of claim 3, further comprising:

notifying the RC mechanism when said entry has been selected for dispatch; and

signaling said RC mechanism when said entry is full.

5. The method of claim 4, further comprising:

automatically resetting said byte enable bits for the entry when the entry is dispatched to an RC machine of said RC mechanism, wherein a full signal is reset to no longer indicate the entry is fill.

6. The method of claim 4, wherein said completing step comprises:

receiving at said RC mechanism an entry select identifying the entry for dispatch;

receiving at said RC mechanism a signal indicating that the entry is full;

assigning the cache line update operation to an RC machine of said RC mechanism;

providing an indication to the RC machine that the entire cache line is being updated.

7. The method of claim 6, further comprising:

responsive to a receipt by said RC machine of the signal indicating that the entry being dispatched is full, activating a cache update mechanism that enables the completion of the cache line update without requiring a copy of the cache line or current data within the cache line, wherein cache line updates from entries that are not full are completed with current copies of the cache line within the cache and write permission to the cache line.

8. The method of claim 1, wherein following a miss at said processor cache or a hit at said processor cache with a cache line that becomes stale prior to completion of said update, said completing step comprises:

issuing an address-only operation to obtain write permission for said cache line; and

automatically updating said cache line with data from said entry once said write permission is obtained.

9. A processor chip for utilization within a data processing system having a memory hierarchy, said processor chip comprising:

a processor core;

a store queue having multiple entries, each entry including registers for storing address and data of store operations issued by the processor core and byte-enable bits, one for each smallest storage granule of data that may be stored by a store operation;

a store queue (STQ) controller that monitors and controls said store queue;

arbitration logic associated with said STQ controller that selects an entry from among multiple eligible entries available for dispatch to be stored in a lower level cache; and

an RC mechanism that perform updates to cache lines within said lower level cache utilizing data from the entry selected for dispatch; and

first logic for determining when all storage granules within a store queue entry have received data from said processor core before said entry is selected for dispatch; and

second logic within an RC machine of said RC mechanism assigned to update a target cache line with data of said entry for completing said update of the target cache line without initiating a data tenure on the system bus, wherein said update is completed regardless of whether said cache line is present in said lower level cache or said cache line data is stale.

10. The processor chip of claim 9, wherein said first logic comprises:

a series of AND logic associated with each of said entries that receives as input a value of each of said byte-enable bits and provides a single AND output that indicated when all said byte-enable bits are set, indicating a full entry.

11. The processor chip of claim 9, said first logic comprising:

means for logically ANDing a value of each bit within said byte enabled register corresponding to said target cache line to generate an AND output;

means for providing said AND output to said STQ controller;

means, when said AND output indicates all bits have been set, for said STQ queue controller to mark said entry as eligible for dispatch.

12. The processor chip of claim 11, wherein when said entry is full and is selected for dispatch, said STQ controller further comprises:

means for signaling said RC mechanism that said entry contains a full set of data to update an entire target cache line; and

means for resetting said byte-enable bits of said entry to track a new gather of store operations.

13. The processor chip of claim 9, wherein said second logic comprises:

means for determining whether the targeted cache line is within said processor cache;

means, when said targeted cache line is within said processor cache, for issuing an address only operation to a system bus requesting write permission for said cache line; and

when said targeted cache line is not within said processor cache and said entire cache line is being updated;

means for issuing an address-only operation on said system bus to obtain write permission and invalidate all other copies of said cache line within other processor caches; and

means for writing said address and data to a line within said processor cache.

14. The processor chip of claim 9, further comprising means for tagging said targeted cache line with a most recently modified coherency state following said update.

15. The processor chip of claim 9, wherein when said entry is not a full entry, said RC machine further comprises:

means for obtaining a copy of said cache line data when said cache line data is not present within said processor cache; and

means for obtaining write permission for said cache line when said write permission is not currently owned by said processor cache, wherein said update is completed only when said cache line data is present in said cache and write permission for the cache line is obtained.

16. A data processing system comprising:

a processor chip having a processor core, store queue (STQ) mechanism, RC mechanism, and associated processor cache;

a memory hierarchy coupled to said processor chip and providing coherent memory operation;

means for completing updates to a cache line of the processor cache with data from processor-issued stores, wherein when all storage granules of said cache line are being updated by a single RC machine tenure, the update is completed without requiring a data tenure on the system bus, regardless of whether the cache line being updated is present in the processor cache or the cache line is present but contains stale data.

17. The data processing system of claim 16, wherein:

said store queue mechanism comprises a store queue that includes a plurality of entries, each entry having at least a data and address register and byte-enable bits; and

said processor chip further includes first logic for determining when a store queue entry selected for dispatch by an provides a complete update to a target cache line of the processor cache; and

said RC mechanism assigned said update includes second logic for completing said update to said target cache line with address-only operations, wherein no data tenure is requested when the target entire cache line is being completely updated.

18. The data processing system of claim 17, wherein said first logic for completing said determination of a full entry comprises:

a series of AND logic associated with each of said entries that receives as input a value of each of said byte-enable bits and provides a single AND output that indicated when all said byte-enable bits are set, indicating a full entry.

19. The data processing system of claim 17, said first logic for determining comprising:

means for logically ANDing a value of each bit within said byte enabled register corresponding to said target cache line to generate an AND output; and

means for providing said AND output to a STQ controller of the store queue mechanism.

20. The data processing system of claim 19, wherein when said entry is full and is selected for dispatch, said STQ controller further comprises:

means for signaling said RC mechanism that said entry contains a full set of data to update an entire target cache line; and

means for resetting said byte-enable bits of said entry to track a new gather of store operations.

21. The data processing system of claim 17, wherein said second logic comprises:

means for determining whether the targeted cache line is within said processor cache;

means, when said targeted cache line is within said processor cache, for issuing an address only operation to a system bus requesting write permission for said cache line; and

when said targeted cache line is not within said processor cache and said entire cache line is being updated;

means for issuing an address-only operation on said system bus to obtain write permission and invalidate all other copies of said cache line within other processor caches; and

means for writing said address and data to a line within said processor cache.

22. The data processing system of claim 21, wherein when said entry is not a full entry, said RC mechanism further comprises:

means for obtaining a copy of said cache line data when said cache line data is not present within said processor cache; and

means for obtaining write permission for said cache line when said write permission is not currently owned by said processor cache, wherein said update is completed only when said cache line data is present in said cache and write permission for the cache line is obtained.