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Method for completing full cacheline stores with address-only bus operations

  • US 20050251623A1
  • Filed: 04/15/2004
  • Published: 11/10/2005
  • Est. Priority Date: 04/15/2004
  • Status: Active Grant
First Claim
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1. In a data processing system having multiple processors each having a processor core, store queue (STQ) mechanism, RC mechanism, and associated processor cache, a method for facilitating cache line updates responsive to processor-issued store operations, said method comprising:

  • determining when a store queue entry selected for dispatch by an RC machine provides an update to an entire cache line; and

    completing said update to said entire cache line with address-only operations, wherein no data tenure is requested when an entire cache line is being overwritten.

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