Systems and methods for task migration

• US 20050251667A1
• Filed: 05/03/2004
• Published: 11/10/2005
• Est. Priority Date: 05/03/2004
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Iwamoto, Tatsuya
• Granted Patent: US 7,437,536 B2
• Time in Patent Office: Days
• US Class Current: 712/233
• CPC Class Codes: G06F 9/4486 Formation of subprogram jump address
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

Methods and systems are provided whereby, in one aspect, pointers to address locations of instructions, static data and dynamically-created data are stored such that the instructions, static data and dynamically-created data can be moved to a different memory or processor without changing the values of the pointers.

Claims

1. A method of processing a task comprising:

providing instructions stored in addressable memory,

providing a base value related to the addresses at which the instructions are stored,

providing a jump instruction to a target instruction wherein the jump instruction includes a parameter value,

processing the jump instruction by jumping to a routine stored in the memory in which the instructions are stored, wherein the routine comprises the steps of;

(a) determining the address of the target instruction based on the parameter value and base value and (b) jumping to the physical address of the target instruction.

2. The method of claim 1 wherein the jump instruction is conditional.

3. The method of claim 1 wherein the jump instruction is unconditional.

4. The method of claim 1 wherein the base value is stored in a register, and the base value is dependent upon the physical address location of one or more of the instructions.

5. The method of claim 4 further comprising providing a task image comprising the instructions, dynamic data created in response to the execution of the instructions, and other data, and wherein base value is dependant upon the lowest physical first address of the task.

6. The method of claim 1 further comprising storing a mask value indicating whether the instructions may be moved to another memory location.

7. The method of claim 1 further comprising masking an interrupt request to move the task during the steps of jumping to a routine stored in the memory and determining the address of the target instruction.

8. The method of claim 7 further comprising unmasking the interrupt request after the steps of jumping to a routine stored in the memory and determining the address of the target instruction.

9. The method of claim 1 wherein the address of the target instruction is determined by summing the parameter value and base value.

10. A method of processing a task comprising:

providing instructions stored in addressable memory, wherein the instructions comprise a jump instruction to a target routine, a return instruction within the target routine, and a subsequent instruction to be executed after the target routine is executed,

providing a first base value related to the addresses at which the instructions are stored,

processing the jump instruction by determining a return value based on the base value and address of the jump instruction, storing the return value, determining the address of the target instruction based on the parameter value and base value, and jumping to the address of the target routine,

changing the addresses at which the instructions are stored and storing a second base value related to the changed addresses,

after the addresses of the instruction are changed, processing the return instruction by determining the address of the subsequent instruction based on the return value and the second base value and jumping to the address.

11. The method of claim 10 wherein the return offset is determined by subtracting the base value from the parameter.

12. The method of claim 10 comprising preventing the step of changing the addresses at which the instructions are stored during the step of processing the jump instruction.

13. The method of claim 12 wherein the preventing step comprises masking an interrupt request to change the address location of the instructions.

14. The method of claim 10 further comprising:

providing a first data base value different from the first and second base value;

creating dynamic data in response to the execution of the instructions, wherein pointers to the data are stored as offsets from the first data base value;

changing the addresses at which the dynamic data is stored but not the values of the pointers;

storing a second data base value related to the changed addresses;

after the addresses of the dynamic data are changed, processing the data access instructions by determining the address of the data based on the pointer value and the second data base value.

15. A system for processing a task comprising:

a plurality of sub-processing units,

instructions executable by the sub-processing unit,

a global base address register for each sub-processing unit, the global base address register storing a global base value,

static data comprising data accessed by a sub-processing unit in response to the instructions and whose values are stored prior to the execution of the instructions,

dynamic data comprising data accessed by a sub-processing unit in response to the instructions and whose values are not stored prior to the execution of the instructions,

jump instructions having parameters, wherein the parameters are independent of the physical address of the instruction to jump to, and

data pointers having parameters, wherein the parameters are independent of the physical address of the data to be accessed,

wherein the jump instructions and data pointers are resolved based on the parameters and the global address value, and wherein moving the instructions from one processor to another processor comprises changing the global base value but not the parameters.

16. The system of claim 15 further comprising a return address register for storing a value related to an address to return to after execution of a routine that was jumped to.

17. The system of claim 15 further comprising an interrupt mask value indicating whether the memory address of the instructions can be changed.

18. The system of claim 15 wherein the instructions are stored in a local memory uniquely associated the sub-processing unit.

19. The system of claim 15 wherein the dynamic data includes a heap and a stack.

20. The system of claim 15 wherein at least some of the pointers are stored as parameters in data access instructions and at least some of the pointers are stored in the dynamic data.

21. The system of claim 20 wherein all of the data pointers created in response to execution of the instructions are contain parameters that are independent of the physical address of the data to be accessed.

22. A method of processing tasks comprising,

storing instructions in an addressable memory accessible by a first processor, the instructions having a first subset of instructions and a second subset of instructions whereby the second subset of instructions access data created by the first subset,

storing a first base value that is related to the physical addresses in which the instructions are stored,

the first processor executing the first subset of the instructions and creating dynamic data in response to such execution, wherein the dynamic data includes a pointer value pointing to target dynamic data,

the first processor accessing the target dynamic data by determining the physical address of the target data based on the first base value and the pointer value,

after the first subset of instructions are executed, storing the instructions and dynamic data in an addressable memory accessible by a second processor without changing the pointer values, and

the second processor executing the second subset of instructions and accessing the target dynamic data based on the second base value and the pointer value.

23. A system of processing a task comprising:

instructions stored in addressable memory,

memory storing a base value related to the addresses at which the instructions are stored,

memory storing a jump instruction to a target instruction wherein the jump instruction includes a parameter value,

means for processing the jump instruction by jumping to a routine stored in the memory in which the instructions are stored, wherein the routine comprises the steps of;

(a) determining the address of the target instruction based on the parameter value and base value and (b) jumping to the physical address of the target instruction.

24. The system of claim 23 wherein the base value is stored in a register, and the base value is dependant upon the physical address location of one or more of the instructions.

25. The system of claim 23 further comprising a task image comprising the instructions, dynamic data created in response to the execution of the instructions, and other data, and wherein the base value is dependant upon the lowest physical first address of the task.

26. The system of claim 23 further comprising a mask value indicating whether the instructions may be moved to another memory location.

27. The system of claim 26 further means for unmasking an interrupt request after the steps of jumping to a routine stored in the memory and determining the address of the target instruction.

28. A system of processing a task comprising:

instructions stored in addressable memory, wherein the instructions comprise a jump instruction to a target routine, a return instruction within the target routine, and a subsequent instruction to be executed after the target routine is executed,

means for providing a first base value related to the addresses at which the instructions are stored,

means for processing the jump instruction by determining a return value based on the base value and address of the jump instruction, storing the return value, determining the address of the target instruction based on the parameter value and base value, and jumping to the address of the target routine, and

means for changing the addresses at which the instructions are stored and storing a second base value related to the changed addresses, such that after the addresses of the instruction are changed, the return instruction is processed by determining the address of the subsequent instruction based on the return value and the second base value and jumping to the address.

29. The system of claim 28 wherein the return offset is determined by subtracting the base value from the parameter.

30. The system of claim 29 further comprising means for preventing the step of changing the addresses at which the instructions are stored during the step of processing the jump instruction.

31. The system of claim 30 wherein the means for preventing comprises means for masking an interrupt request to change the address location of the instructions.

32. The system of claim 29 further comprising:

means for providing a first data base value different from the first and second base value;

means for creating dynamic data in response to the execution of the instructions, wherein pointers to the data are stored as offsets from the first data base value;

means for changing the addresses at which the dynamic data is stored but not the values of the pointers;

means for storing a second data base value related to the changed addresses;

means for processing the data access instructions by determining the address of the data based on the pointer value and the second data base value after the addresses of the dynamic data is changed.

33. A system for processing tasks comprising:

a first processor;

a first memory associated with the first processor;

a first base register containing a value related to the physical address location of the task image when loaded in the first memory;

a second processor;

a second memory associated with the second processor;

a second base register containing a value related to the physical address location of the task image when loaded in the second memory;

a task image comprising jump instructions having parameters, data access instructions having parameters, static data created prior to execution of the instructions by the first processor, a heap created in response to execution of the instructions by the first processor and comprising parameters, and a stack, wherein the parameters depend on the location of instructions or data; and

an address resolution routine executed in response to the execution of a jump instruction or data access instruction, the address resolution routine for determining a physical address based on the register value associated with the processor executing the instructions or accessing the data, and the parameter of the jump instruction or data access instruction;

wherein the task image, including the parameter values as stored in the first memory, is copied from the first memory to the second memory in response to an interrupt request.

34. The system of claim 33 further comprising an interrupt mask register containing a mask value indicating whether the task image may be copied from the first memory to the second processor in response to an interrupt, wherein the interrupt is masked during at least a portion of the address resolution routine.

35. The system of claim 34 wherein the address resolution routine further comprises instructions for calculating a return value based on the address of the jump instruction and the value of the first or second base register depending on whether the first or second processor is executing the jump instruction;

and a return address resolution routine executed in response to the execution of a return instruction for determining the physical address of the instruction to be executed after the jump instruction, the physical address being determined based on the return value and the value of the first or second base register depending on whether the first or second processor is executing the return instruction.

36. The system of claim 34 further comprising a third processor for copying the task image from the first memory to the second memory in response to an interrupt request.

37. The system of claim 36 wherein the third processor is a processing unit and the first and second processors are sub-processors.