Systems and methods for task migration
First Claim
Patent Images
1. A method of processing a task comprising:
- providing instructions stored in addressable memory, providing a base value related to the addresses at which the instructions are stored, providing a jump instruction to a target instruction wherein the jump instruction includes a parameter value, processing the jump instruction by jumping to a routine stored in the memory in which the instructions are stored, wherein the routine comprises the steps of;
(a) determining the address of the target instruction based on the parameter value and base value and (b) jumping to the physical address of the target instruction.
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Abstract
Methods and systems are provided whereby, in one aspect, pointers to address locations of instructions, static data and dynamically-created data are stored such that the instructions, static data and dynamically-created data can be moved to a different memory or processor without changing the values of the pointers.
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Citations
37 Claims
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1. A method of processing a task comprising:
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providing instructions stored in addressable memory, providing a base value related to the addresses at which the instructions are stored, providing a jump instruction to a target instruction wherein the jump instruction includes a parameter value, processing the jump instruction by jumping to a routine stored in the memory in which the instructions are stored, wherein the routine comprises the steps of;
(a) determining the address of the target instruction based on the parameter value and base value and (b) jumping to the physical address of the target instruction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of processing a task comprising:
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providing instructions stored in addressable memory, wherein the instructions comprise a jump instruction to a target routine, a return instruction within the target routine, and a subsequent instruction to be executed after the target routine is executed, providing a first base value related to the addresses at which the instructions are stored, processing the jump instruction by determining a return value based on the base value and address of the jump instruction, storing the return value, determining the address of the target instruction based on the parameter value and base value, and jumping to the address of the target routine, changing the addresses at which the instructions are stored and storing a second base value related to the changed addresses, after the addresses of the instruction are changed, processing the return instruction by determining the address of the subsequent instruction based on the return value and the second base value and jumping to the address. - View Dependent Claims (11, 12, 13, 14)
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15. A system for processing a task comprising:
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a plurality of sub-processing units, instructions executable by the sub-processing unit, a global base address register for each sub-processing unit, the global base address register storing a global base value, static data comprising data accessed by a sub-processing unit in response to the instructions and whose values are stored prior to the execution of the instructions, dynamic data comprising data accessed by a sub-processing unit in response to the instructions and whose values are not stored prior to the execution of the instructions, jump instructions having parameters, wherein the parameters are independent of the physical address of the instruction to jump to, and data pointers having parameters, wherein the parameters are independent of the physical address of the data to be accessed, wherein the jump instructions and data pointers are resolved based on the parameters and the global address value, and wherein moving the instructions from one processor to another processor comprises changing the global base value but not the parameters. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A method of processing tasks comprising,
storing instructions in an addressable memory accessible by a first processor, the instructions having a first subset of instructions and a second subset of instructions whereby the second subset of instructions access data created by the first subset, storing a first base value that is related to the physical addresses in which the instructions are stored, the first processor executing the first subset of the instructions and creating dynamic data in response to such execution, wherein the dynamic data includes a pointer value pointing to target dynamic data, the first processor accessing the target dynamic data by determining the physical address of the target data based on the first base value and the pointer value, after the first subset of instructions are executed, storing the instructions and dynamic data in an addressable memory accessible by a second processor without changing the pointer values, and the second processor executing the second subset of instructions and accessing the target dynamic data based on the second base value and the pointer value.
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23. A system of processing a task comprising:
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instructions stored in addressable memory, memory storing a base value related to the addresses at which the instructions are stored, memory storing a jump instruction to a target instruction wherein the jump instruction includes a parameter value, means for processing the jump instruction by jumping to a routine stored in the memory in which the instructions are stored, wherein the routine comprises the steps of;
(a) determining the address of the target instruction based on the parameter value and base value and (b) jumping to the physical address of the target instruction. - View Dependent Claims (24, 25, 26, 27)
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28. A system of processing a task comprising:
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instructions stored in addressable memory, wherein the instructions comprise a jump instruction to a target routine, a return instruction within the target routine, and a subsequent instruction to be executed after the target routine is executed, means for providing a first base value related to the addresses at which the instructions are stored, means for processing the jump instruction by determining a return value based on the base value and address of the jump instruction, storing the return value, determining the address of the target instruction based on the parameter value and base value, and jumping to the address of the target routine, and means for changing the addresses at which the instructions are stored and storing a second base value related to the changed addresses, such that after the addresses of the instruction are changed, the return instruction is processed by determining the address of the subsequent instruction based on the return value and the second base value and jumping to the address. - View Dependent Claims (29, 30, 31, 32)
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33. A system for processing tasks comprising:
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a first processor;
a first memory associated with the first processor;
a first base register containing a value related to the physical address location of the task image when loaded in the first memory;
a second processor;
a second memory associated with the second processor;
a second base register containing a value related to the physical address location of the task image when loaded in the second memory;
a task image comprising jump instructions having parameters, data access instructions having parameters, static data created prior to execution of the instructions by the first processor, a heap created in response to execution of the instructions by the first processor and comprising parameters, and a stack, wherein the parameters depend on the location of instructions or data; and
an address resolution routine executed in response to the execution of a jump instruction or data access instruction, the address resolution routine for determining a physical address based on the register value associated with the processor executing the instructions or accessing the data, and the parameter of the jump instruction or data access instruction;
wherein the task image, including the parameter values as stored in the first memory, is copied from the first memory to the second memory in response to an interrupt request. - View Dependent Claims (34, 35, 36, 37)
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Specification