Method and base chip for monitoring the operation of a microcontroller unit

• US 20050251704A1
• Filed: 06/04/2003
• Published: 11/10/2005
• Est. Priority Date: 06/10/2002
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Muth, Mathias, Wagner, Martin
• Application Number:
  US10/517,109
• Publication Number:
  US 20050251704A1
• Time in Patent Office: Days
• US Class Current: 714/47
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing

Abstract

To enable a method and a base chip (200) for monitoring the operation of at least one microcontroller unit (300) that is intended for at least one application and is associated with a system (100) to bc further developed in such a way that the operation of the microcontroller unit (300), which is associated with a serial system, is monitored in such a way as to enable faulty operation, and particularly faulty operation that discharges the battery, to be reliably prevented, it is proposed that the microcontroller unit (300) has at least one non-volatile memory area (10) associated with it, the memory area (10) can be read from and/or written to by the microcontroller unit (300), and at least one set of statistics, and in particular a set of fault statistics, relating to the operation of the microcontroller unit (300), can be kept by means of the memory area (10).

Claims

1. A method of monitoring the operation of at least one microcontroller unit (300) that is intended for at least one application and is associated with a system (100), characterized in that

the microcontroller unit (300) has at least one non-volatile memory area (10) associated with it,

the memory area (10) can be read from and/or written to by the microcontroller unit (300), and

at least one set of statistics, and in particular a set of fault statistics, relating to the operation of the microcontroller unit (300), can be kept by means of the memory area (10).

2. A method as claimed in claim 1, characterized in that the memory area (10) is permanently supplied by at least one battery unit (400).

3. A method as claimed in claim 1 or 2, characterized in that,

in relation to the operation of the microcontroller unit (300), a distinction can be made between different reset events and in that

these different reset events can be made accessible to the microcontroller unit (300).

4. A method as claimed in any of claims 1 to 3, characterized in that the memory area (10)

can be read from at any time and/or

can be written to only after a reset or while the system (100) is restarting.

10. Use of a method as claimed in any of claims 1 to 4 and/or of at least one base chip (200) as claimed in any of claims 5 to 8 for monitoring the operation of at least one microcontroller unit (300) intended for at least one application, in automobile electronics and in particular in the electronics of motor vehicles.

5. A base chip (200), and particularly a system base chip, for monitoring the operation of at least one microcontroller unit (300) that is intended for at least one application, characterized by at least one non-volatile memory area (10) that can be read from and/or written to by the microcontroller unit (300), and by means of which at least one set of statistics, and particularly at least one set of fault statistics, can be produced relating to the operation of the microcontroller unit (300).

6. A base chip as claimed in claim 5, characterized by

at least one information unit (20) that is provided to allow for different reset events,

at least one reset unit (40) for resetting the microcontroller unit (300), which reset unit (40) is connected (42) to the microcontroller unit (300), and

at least one supply unit (50) that is connected (52) to the microcontroller unit (300).

7. A base chip as claimed in claim 6, characterized in that

the memory area (10) and the supply unit (50) are permanently associated with at least one battery unit (400), and in that

the microcontroller unit (300) has at least one temporary energy supply associated with it via the supply unit (50).

8. A base chip as claimed in any of claims 5 to 7, characterized in that the memory area (10) and/or the information unit (20) have inserted in front of them at least one interface unit (30) for the exchange of data with the microcontroller unit (300).

9. A system (100), and particularly a control system, characterized by at least one microcontroller unit (300) intended for at least one application and by at least one base chip (200) as claimed in any of claims 5 to 8.