Microprocessor comprising error detection means protected against an attack by error injection
First Claim
1. A method for monitoring an execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes, the method comprising:
- during the execution of the sequence, producing current cumulative signatures that vary according to logic signals taken off in the integrated circuit, until, at an end of the execution of the sequence, a final cumulative signature is obtained;
during the execution of the sequence, producing an error signal having an active value by default and remaining on the active value while the current cumulative signature is different from an expected signature;
masking the error signal for a time interval corresponding substantially to a presumed duration of execution of the sequence; and
unconditionally lifting the masking of the error signal when the time interval expires.
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Accused Products
Abstract
A method for monitoring the execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes. In one embodiment, the method comprises producing current cumulative signatures during the execution of a sequence, until a final cumulative signature is obtained, producing an error signal having a value active by default while the current cumulative signature is different to an expected signature, measuring a predetermined time interval that is substantially longer than the presumed duration of execution of the sequence, masking the error signal during the measurement of the time interval, and lifting the masking of the error signal when the time interval expires.
65 Citations
49 Claims
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1. A method for monitoring an execution of a sequence of instruction codes in an integrated circuit comprising a central processing unit provided for executing such instruction codes, the method comprising:
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during the execution of the sequence, producing current cumulative signatures that vary according to logic signals taken off in the integrated circuit, until, at an end of the execution of the sequence, a final cumulative signature is obtained;
during the execution of the sequence, producing an error signal having an active value by default and remaining on the active value while the current cumulative signature is different from an expected signature;
masking the error signal for a time interval corresponding substantially to a presumed duration of execution of the sequence; and
unconditionally lifting the masking of the error signal when the time interval expires. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a central processing unit for executing a program comprising instruction codes; and
means for monitoring an execution of at least one sequence of instruction codes comprising at least one instruction code, the monitoring means comprising;
a signature calculation circuit for producing current cumulative signatures that vary according to logic signals of the integrated circuit, the signature calculation circuit supplying, at an end of the execution of the sequence, a final cumulative signature;
means for storing an expected signature;
a timer for measuring a time interval;
means for producing an error signal having an active value by default as soon as the execution of the sequence starts, and remaining on the active value while the current cumulative signature is different to the expected signature; and
means for masking the error signal during the measurement of the time interval by the timer, and unconditionally lifting the error signal when the time interval expires. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A computer-readable memory medium containing a sequence of instructions for controlling an integrated circuit, the sequence including instructions for causing the integrated circuit to:
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store an expected final cumulative signature; and
store a value corresponding to an expected duration of an execution of the sequence of instructions. - View Dependent Claims (19, 20, 21, 22)
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23. An integrated circuit, comprising:
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a processor for executing a sequence of instruction codes;
a signature production module configured to produce cumulative signatures during the execution of the sequence of instructions;
an error detector coupled to the signature production module and configured to generate an error signal when a current cumulative signature is different from an expected signature; and
an error masking module configured to mask the error signal generated by the error detector when the current cumulative signature is expected to be different from the expected signature. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. A method of detecting error injection during execution of a sequence of instruction codes by an integrated circuit, comprising:
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masking an error signal;
activating the error signal;
executing the sequence of instruction codes;
generating a cumulative signature during execution of the sequence of instruction codes;
deactivating the error signal when a cumulative signature is equal to an expected final cumulative signature; and
lifting the mask when the cumulative signature is expected to be equal to the final cumulative signature. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38)
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39. A system comprising:
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a smart card; and
an electronic device coupled to the smart card, wherein the system includes an integrated circuit, the integrated circuit comprising;
a processor for executing a sequence of instruction codes;
a signature production module configured to produce a current cumulative signature during execution of the sequence of instructions;
an error detection module coupled to the signature production module and configured to produce an error signal based on a comparison of the current cumulative signature with an expected final cumulative signature; and
an error masking module coupled to the error detection module and configured to mask the error signal until the cumulative signature is expected to be equal to the final cumulative signature. - View Dependent Claims (40, 41, 42, 43, 44)
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45. An integrated circuit, comprising:
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means for executing a sequence of instructions;
means for producing a current cumulative signature during execution of the sequence of instructions;
means for comparing the current cumulative signature with an expected signature; and
means for masking an output of the means for comparing the current cumulative signature with the expected signature. - View Dependent Claims (46, 47, 48, 49)
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Specification