Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling

• US 20050251765A1
• Filed: 05/10/2004
• Published: 11/10/2005
• Est. Priority Date: 05/10/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Ahmad, Faisal A., Patel, Anish T.
• Granted Patent: US 7,426,704 B2
• Time in Patent Office: Days
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability. This includes generating a plurality of possible combinations of input stimulus sequences and generating an array representation of critical resource requirements. These are used to generate an array representation of critical resources availabilities.

Claims

1. A method of generating valid random input stimulus sequences for a logic circuit model comprising:

a. enumerating critical resource requirements;

b. enumerating critical resource availabilities;

c. selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability.

2. The method of claim 1 comprising generating a plurality of possible combinations of input stimulus sequences.

3. The method of claim 1 comprising generating an array representation of critical resource requirements.

4. The method of claim 1 comprising generating an array representation of critical resources availabilities.

5. The method of claim 1 comprising:

a. generating an array representation of critical resource requirements;

b. generating an array representation of critical resources availabilities;

c. generating a plurality of possible combinations of input stimulus sequences; and

d. applying an input stimulus sequence to the logic circuit model.

6. The method of claim 5 comprising weighting the input sequence and generating input sequences having a biased probability distribution.

7. The method of claim 6 comprising statistically biasing input sequence execution times.

8. The method of claim 1 comprising generating a parameterized representation of model resources for customizing critical resource usage information for a given stimulus according to configuration data.

9. A method of generating valid random input stimulus sequences for a logic circuit model and testing the circuit model comprising:

a. initializing the logic circuit model;

b. calculating resource usage;

c. selecting a command;

d. parsing resource usage of the selected command, determining available times to issue the selected command, and executing the command;

e. proceeding to a next command and determining available times to issue the command;

f. parsing resource availability of the command for an available time to execute the command;

g. if no available time, pausing the command and resending the command;

h. if there is an available time, selecting an optimal window within which to send the command;

i. scheduling the command;

j. executing the command; and

k. choosing a next command if a next command exists, and wherein if the next command is part of a list selecting the next command sequentially or randomly, else exiting.

10. The method of claim 9 comprising initializing the logic circuit model by choosing a behavior modifying option chosen from the group consisting of at least one of the DIMM technology, burst mode, data flow mode, latency setting, and combinations thereof, and initializing the hardware model of the logic circuit.

11. The method of claim 9 comprising calculating resource usage information by the method comprising

a. generating an array representation of critical resource requirements;

b. generating an array representation of critical resources availabilities; and

c. generating a plurality of possible combinations of input stimulus sequences.

12. The method of claim 11 comprising applying the input stimulus sequence to the logic circuit model.

13. A system for generating an array representation of critical resource requirements;

b. generating an array representation of critical resources availabilities;

c. generating a plurality of possible combinations of input stimulus sequences; and

d. applying an input stimulus sequence to the logic circuit model.

14. The system of claim 13 adapted for generating a plurality of possible combinations of input stimulus sequences.

15. The system of claim 13 adapted for generating an array representation of critical resource requirements.

16. The system of claim 13 adapted for generating an array representation of critical resources availabilities.

17. The system of claim 13 comprising:

a. generating an array representation of critical resource requirements;

b. generating an array representation of critical resources availabilities;

c. generating a plurality of possible combinations of input stimulus sequences; and

d. applying an input stimulus sequence to the logic circuit model.

18. The system of claim 13 comprising weighting means for the input sequence and for generating sequences having a biased probability distribution from the weighting means;

19. The system of claim 13 comprising means for statistically biasing of the times for execution

20. The system of claim 13 comprising means for parameterized representation of model resources for customizing critical resource usage information for a stimulus according to model configuration

21. A system for generating valid random input stimulus sequences for a logic circuit model and testing the circuit model comprising:

a. initializing the logic circuit model;

b. calculating resource usage;

c. selecting a command;

d. parsing resource usage of the selected command, determining available times to issue the selected command, and executing the command;

e. proceeding to a next command and determining available times to issue the command;

f. parsing resource availability of the command for an available time to execute the command;

g. if no available time, pausing the command and resending the command;

h. if there is an available time, selecting an optimal window within which to send the command;

i. scheduling the command;

j. executing the command; and

k. choosing a next command if a next command exists, and wherein if the next command is part of a list selecting the next command sequentially or randomly else exiting.

22. The system of claim 21 adapted for initializing the logic circuit model by choosing a behavior modifying option chosen from the group consisting of at least one of the DIMM technology, burst mode, data flow mode, latency setting, and combinations thereof, and initializing the hardware model of the logic circuit.

23. The system of claim 22 adapted for calculating resource usage information by the method comprising

a. generating an array representation of critical resource requirements;

b. generating an array representation of critical resources availabilities; and

c. generating a plurality of possible combinations of input stimulus sequences.

24. The system of claim 23 adapted for applying the input stimulus sequence to the logic circuit model.

25. A program product comprising computer readable computer code for carrying out a method of generating valid random input stimulus sequences for a logic circuit model comprising:

a. enumerating critical resource requirements;

b. enumerating critical resource availabilities;

c. selecting of stimulus sequences and determining legal times for execution of said stimulus sequences based on resource availability.

26. The program product of claim 25 comprising program code for generating a plurality of possible combinations of input stimulus sequences.

27. The program product of claim 25 comprising program code for generating an array representation of critical resource requirements.

28. The program product of claim 25 comprising program code for generating an array representation of critical resources availabilities.

29. The program product of claim 28 comprising program code for:

a. generating an array representation of critical resource requirements;

b. generating an array representation of critical resources availabilities;

c. generating a plurality of possible combinations of input stimulus sequences; and

d. applying an input stimulus sequence to the logic circuit model.

30. The program product of claim 25 comprising program code for weighting said input sequence and generating sequences having a biased probability distribution from said weighting means;

31. The program product of claim 25 comprising program code for statistically biasing the times for execution

32. The program product of claim 25 comprising program code for parameterized representation of model resources for customizing critical resource usage information for a given stimulus according to configuration

33. A program product having computer readable computer code for generating valid random input stimulus sequences for a logic circuit model and testing the circuit model comprising:

a. initializing the logic circuit model;

b. calculating resource usage;

c. selecting a command;

d. parsing resource usage of the selected command, determining available times to issue the selected command, and executing the command;

e. proceeding to a next command and determining available times to issue the command;

f. parsing resource availability of the command for an available time to execute the command;

g. if no available time, pausing the command and resending the command;

h. if there is an available time, selecting an optimal window within which to send the command;

i. scheduling the command;

j. executing the command; and

k. choosing a next command if a next command exists, and wherein if the next command is part of a list selecting the next command sequentially or randomly, else exiting.

34. The program product of claim 33 comprising program code for initializing the logic circuit model by one of choosing the DIMM technology, choosing the burst mode, choosing the data flow mode, choosing latency setting, and initializing the hardware model of the logic circuit.

35. The program product of claim 33 comprising program code for calculating resource usage information by the method comprising

a. generating an array representation of critical resource requirements;

b. generating an array representation of critical resources availabilities; and

c. generating a plurality of possible combinations of input stimulus sequences.

36. The program product of claim 35 comprising program code for applying the input stimulus sequence to the logic circuit model.