Method of forming silicided gate structure

• US 20050253204A1
• Filed: 05/13/2004
• Published: 11/17/2005
• Est. Priority Date: 05/13/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shieh, Jyu-Horng, Tao, Hun-Jan, Chan, Bor-Wen
• Granted Patent: US 7,241,674 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain

Abstract

A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

Claims

1. A method of forming a silicided gate on a substrate having active regions, comprising the steps of:

forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided;

forming a shielding layer over the active regions and gate after said silicide forming step;

forming a coating layer over portions of the shielding layer over the active regions;

opening said shielding layer to expose said gate, wherein said coating layer protects said portions of said shielding layer over said active regions during said opening step;

depositing a metal layer over the exposed gate; and

annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

2. The method of claim 1, further comprising the step of removing said coating layer after said opening step and before said metal depositing step,

wherein the shielding material prevents said metal from reacting with the active regions during said annealing step.

3. The method of claim 2, wherein said removing step comprises an oxygen plasma ashing process.

4. The method of claim 1, wherein said metal layer depositing step comprises depositing said metal layer over the gate a sufficient thickness to fully silicidize the remaining portion of the gate upon annealing.

5. The method of claim 1, wherein the height of the gate is between about 500-2800 Å

.

6. The method of claim 1, wherein said metal is selected from the group consisting of Ni, Co, Pd, Ti and Cr.

7. The method of claim 1, wherein said opening step comprises an etching process.

8. The method of claim 1, wherein said coating layer comprises a polymer.

9. The method of claim 8, wherein the step of forming said coating layer comprises the step of depositing said polymer to a thickness less than the height of said gate, wherein said shielding layer is exposed over a top surface of said gate.

10. The method of claim 8, wherein the step of forming said coating layer comprises:

depositing said polymer over said substrate to a thickness sufficient to cover said gate; and

etching said deposited polymer to a thickness less than the height of said gate, wherein said shielding layer is exposed over a top surface of the gate electrode.

11. The method of claim 8, wherein said polymer comprises a photoresist and the step of forming said coating layer comprises:

depositing said photoresist and developing said photoresist to a thickness less than the height of said gate, wherein said shielding layer is exposed over a top surface of the gate electrode.

12. The method of claim 1, wherein said annealing step comprises annealing to cause the metal to react with the gate to silicidize the remaining portion of the gate, whereby a fully silicided gate is formed.

13. A method of forming a fully silicided gate on a substrate having active regions, comprising the steps of:

forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided;

forming a shielding layer over the active regions and gate after said silicide forming step;

forming a polymer coating over the shielding layer over the active regions to a thickness less than the height of said gate;

etching said shielding layer to expose a top surface of said gate, wherein said polymer coating protects portions of said shielding layer over said active regions from said etching step;

after said etching step, removing said polymer coating over said active regions,

depositing a metal layer over the top surface of said gate; and

annealing to cause the metal to react with the gate to silicidize the remaining portion of the gate, wherein said shielding layer prevents said metal from reacting with the active regions during the annealing, whereby a fully silicided gate is formed

14. The method of claim 13, wherein said polymer coating comprises an organic polymer and said removing step comprising an oxygen plasma ashing process.

15. The method of claim 13, wherein said metal layer deposition step comprises depositing said metal layer over the gate a sufficient thickness to fully silicidize the remaining portion of said gate.

16. The method of claim 13, wherein the height of the gate is between about 1000-2000 Å

.

17. The method of claim 13, wherein said metal is selected from the group consisting of Ni, Co, Pd, Ti and Cr.

18. The method of claim 13, wherein said polymer comprises an organic polymer and the step of forming said coating layer comprises depositing said polymer to a thickness less than the height of said gate, wherein said shielding layer is exposed over a top surface of said gate.

19. The method of claim 13, wherein the polymer comprises an organic polymer and wherein the step of forming said coating layer comprises:

depositing said polymer over said substrate to a thickness sufficient to cover said gate; and

etching said deposited photoresist to a thickness less than the height of said gate, wherein said shielding layer is exposed over a top surface of the gate electrode.

20. The method of claim 13, wherein said polymer comprises a photoresist and the step of forming said coating layer comprises:

depositing said photoresist and developing said photoresist to a thickness less than the height of said gate, wherein said shielding layer is exposed over a top surface of the gate electrode.

21. A method of forming a fully silicided gate on a substrate having active regions, comprising the steps of:

forming silicide in at least the active regions;

depositing a shielding layer over the active regions and gate after said silicide forming step;

forming a coating layer over portions of the shielding layer over the active regions;

etching said shielding layer to expose said gate, wherein said coating layer protects said portions of said shielding layer over said active regions during said opening step;

depositing a metal layer over the exposed gate; and

annealing to cause the metal to react with the gate, wherein a fully silicided gate is formed.

22. A method of forming a silicided gate on a substrate having active regions, comprising the steps of:

forming silicide in the active regions, wherein the gate is unsilicided thereafter;

forming a shielding layer over the active regions and gate after said silicide forming step;

forming a coating layer over portions of the shielding layer over the active regions;

opening said shielding layer to expose said gate, wherein said coating layer protects said portions of said shielding layer over said active regions during said opening step;

depositing a metal layer over the exposed gate; and

annealing to cause the metal to react with the gate to form a silicide in at least a part of the gate.

23. The method of claim 22, wherein said opening step comprises etching said shielding layer to expose a top surface of said gate, wherein said coating layer protects portions of said shielding layer over said active regions from said etching step.

24. The method of claim 22, wherein the depositing step comprises depositing said metal layer over the gate a sufficient thickness to fully silicidize the gate upon annealing, and

wherein said annealing step comprises annealing to cause the metal to react with the gate to fully silicidize the gate.

25. An integrated circuit comprising a substrate having a plurality of gates formed thereon in a patterned region, at least some of said gates formed in an area of relative dense patterning in said patterned region and at least some of said gates formed in an area of relative non-dense patterning in said patterned region, and associated active regions formed therein, said active regions having a silicide formed therein and said gates having a silicide formed therein, wherein said gate silicide is thicker than said silicide formed in said active regions, wherein a gate height difference between said gates in said patterned region is less than 10%.

26. The integrated circuit of claim 25, wherein at least some of said gates are fully silicided.