Chip embedded package structure

• US 20050253244A1
• Filed: 11/18/2004
• Published: 11/17/2005
• Est. Priority Date: 05/11/2004
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chang, Wen-Yuan
• Granted Patent: US 7,170,162 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/83132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A chip embedded package structure is provided. A stiffener is disposed on a tape. The tape has at least an alignment mark and the stiffener has at least a chip opening. A chip having a plurality of bonding pads thereon is disposed on the tape within the chip opening such that the bonding pads face the tape. A plurality of through holes is formed in the tape to expose the bonding pads respectively. After that, an electrically conductive material is deposited to fill the through holes and form a plurality of conductive vias that connects with the bonding pads respectively. A multi-layered interconnection structure is formed on the surface of the tape away from the chip. The multi-layered interconnection structure has an inner circuit that connects to the conductive vias. The inner circuit has a plurality of metallic pads disposed on the outer surface of the multi-layered interconnection structure.

Claims

1. A chip embedded package structure, comprising:

a tape, having at least a first alignment mark disposed on a surface of the tape, wherein the tape comprises a plurality of conductive vias passing through the tape;

a stiffener, disposed on the tape, wherein the stiffener comprises at least a chip opening;

at least a chip, disposed on the tape inside the chip opening such that an active surface of the chip faces the tape, wherein the chip also comprises a plurality of bonding pads disposed on the active surface and the bonding pads are electrically connected to the conductive vias respectively; and

a multi-layered interconnection structure, disposed on the surface of the tape away from the chip, wherein the multi-layered interconnection structure comprises an inner circuit connecting with the conductive vias and comprises a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.

2. The chip embedded package structure of claim 1, wherein the first alignment mark is located under the chip opening.

3. The chip embedded package structure of claim 1, wherein the first alignment mark is located on the surface of the tape on the same side as the chip.

4. The chip embedded package structure of claim 1, wherein the first alignment mark is located on the surface of the tape away from the chip.

5. The chip embedded package structure of claim 4, wherein the tape further comprises at least a second alignment mark disposed on the surface of the tape on the same side as the chip.

6. The chip embedded package structure of claim 1, wherein the tape is fabricated using a transparent material.

7. The chip embedded package structure of claim 1, wherein the tape further comprises a circuit layer disposed on the surface of the tape away from the chip and connected to the conductive vias and the inner circuit.

8. The chip embedded package structure of claim 1, wherein the package further comprises a plurality of conductive balls disposed on the metallic pads respectively.

9. The chip embedded package structure of claim 1, wherein the package further comprises a plurality of conductive pins disposed on the metallic pads respectively.

10. The chip embedded package structure of claim 1, wherein the package further comprises an encapsulating compound disposed inside the chip opening between the chip and the stiffener.

11. An electronic system for disposing on a circuit board, comprising:

a bus;

a memory unit, connected to the bus;

a chip embedded package structure, connected to the bus, wherein the chip embedded package structure further comprises;

a tape, having at least a first alignment mark disposed on a surface of the tape, wherein the tape comprises a plurality of conductive vias passing through the tape;

at least a stiffener, disposed on the tape, wherein the stiffener comprises at least a chip opening;

a chip, disposed on the tape inside the chip opening such that an active surface of the chip faces the tape, wherein the chip also comprises a plurality of bonding pads disposed on the active surface and the bonding pads are electrically connected to the conductive vias respectively; and

a multi-layered interconnection structure, disposed on the surface of the tape away from the chip, wherein the multi-layered interconnection structure comprises an inner circuit that connects with the conductive vias and comprises a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.

12. The electronic system of claim 11, wherein the first alignment mark is disposed under the chip opening.

13. The electronic system of claim 11, wherein the first alignment mark is disposed on the surface of the tape on the same side as the chip.

14. The electronic system of claim 11, wherein the first alignment mark is disposed on the surface of the tape away from the chip.

15. The electronic system of claim 14, wherein the tape further comprises at least a second alignment mark disposed on the surface of the tape on the same side as the chip.

16. The electronic system of claim 11, wherein the tape is fabricated using a transparent material.

17. The electronic system of claim 11, wherein the tape further comprises a circuit layer disposed on the surface of the tape away from the chip and connected to the conductive vias and the inner circuit.

18. The electronic system of claim 11, wherein the chip embedded package structure further comprises a plurality of conductive balls disposed on the metallic pads respectively.

19. The electronic system of claim 11, wherein the chip embedded package structure further comprises a plurality of conductive pins disposed on the metallic pads respectively.

20. The electronic system of claim 11, wherein the chip embedded package structure further comprises an encapsulating compound disposed within the chip opening between the chip and the stiffener.

21. The electronic system of claim 11, wherein the system further comprises at least a power supply unit that connects with the bus.

22. The electronic system of claim 11, wherein the system further comprises a microprocessor connected to the bus.

23. The electronic system of claim 11, wherein the chip is a microprocessor.

24. The electronic system of claim 11, wherein the electronic system is a computer system.

25. The electronic system of claim 11, wherein the electronic system is a communication chip system.