System and method for testing integrated circuits

• US 20050253617A1
• Filed: 05/03/2004
• Published: 11/17/2005
• Est. Priority Date: 05/03/2004
• Status: Active Grant

• Current Assignee: DFT Microsystems, Inc.
• Original Assignee: DFT Microsystems Canada, Inc.
• Inventors: Roberts, Gordon W., Pishdad, Bardia, Duerden, Geoffrey D., Tam, Clarence K.L., Hafed, Mohamed M., Chan, Antonio H., Laberge, Sebastien
• Granted Patent: US 7,242,209 B2
• Time in Patent Office: Days
• US Class Current: 324/756.20
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924

Abstract

A module (236, 236′) containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).

Claims

1. An integrated testing system for testing circuitry of a DUT via an interface board having a first socket for receiving the integrated testing system and a second socket for receiving the DUT, the integrated testing system comprising:

a module operatively configured to engage the first socket of the interface board and including;

a) at least one measurement engine operatively configured to electrically excite the circuitry, measure a response of the circuitry and generate measurement data when the integrated testing system is engaged with the first socket and the DUT is engaged with the second socket; and

b) a compute engine operatively configured to perform at least one computation on said measurement data.

2. An integrated testing system according to claim 1, wherein said compute engine is operatively configured to determine whether the DUT passes or fails.

3. An integrated testing system according to claim 1, wherein said at least one measurement engine comprises a plurality of stimulus instruments each operatively configured to provide a corresponding stimulus signal to the DUT.

4. An integrated testing system according to claim 1, wherein said at least one measurement engine comprises a plurality of measurement engines each operatively configured to measure a corresponding response signal output by the DUT.

5. An integrated testing system according to claim 1, wherein said compute engine further comprises a micro-code processor operatively configured to execute one or more programs that control said at least one measurement instrument and said compute engine so that the integrated testing system performs the testing.

6. An integrated testing system according to claim 1, wherein said at least one measurement engine includes at least one RLD and said compute engine contains a microcontroller operatively configured to program said at least one RLD.

7. An integrated testing system according to claim 1, wherein said compute engine includes at least one RLD and a microcontroller operatively configured to program said at least one RLD.

8. An integrated testing system according to claim 1, further comprising a communications engine aboard said module and operatively coupled with said compute engine.

9. An integrated testing system according to claim 8, wherein said communications engine is operatively configured to facilitate communications between ATE and said compute engine.

10. An integrated testing system according to claim 9, wherein the ATE includes a data vector communications link and said communications engine is operatively configured to communicate over the data vector communications link.

11. An integrated testing system according to claim 8, wherein said compute engine is operatively configured to receive instructions via said communications link for conducting testing.

12. An integrated testing system according to claim 8, wherein at least one of said compute engine and said at least one measurement engine includes an RLD and said compute engine is operatively configured to receive instructions via said communications engine for programming said RLD.

13. An integrated testing system according to claim 8, wherein the integrated testing system is controllable via a non-ATE user interface and said communications engine is operatively configured to facilitate communications between the non-ATE user interface and said compute engine.

14. An integrated testing system according to claim 1, further comprising a host computer containing a user interface operatively configured to control the integrated testing system.

15. An integrated testing system according to claim 14, wherein said host computer comprises a network server operatively configured to connect to a network of computers.

16. An integrated testing system according to claim 15, wherein said network server is a Web server.

17. An integrated testing system according to claim 1, wherein said compute engine is operatively configured to perform computations on said measurement data substantially in parallel with said at least one measurement engine measuring the response of the circuitry of the DUT.

18. An integrated testing system according to claim 1, further comprising at least one digital link operatively configured to permit said compute engine to communicate digital data to the DUT when the DUT is engaged with the second socket of the interface board.

19. An integrated testing system for testing circuitry of a DUT via an interface board having a first socket for receiving the integrated testing system and a second socket for receiving the DUT, the integrated testing system comprising:

a module operatively configured to engage the first socket of the interface board and including;

a) at least one measurement engine operatively configured to electrically excite the circuitry, measure a response of the circuitry and generate measurement data when the integrated testing system is engaged with the first socket and the DUT is engaged with the second socket;

b) a compute engine operatively configured to perform at least one computation on said measurement data; and

c) a communications engine operatively configured to establish a two-way communications link between said compute engine and at least one device.

20. A testing module according to claim 19, wherein the at least one device is a piece of ATE.

21. An integrated testing system according to claim 19, wherein the at least one device is a host computer containing a user interface for the integrated testing system.

22. An integrated testing system according to claim 21, wherein said host computer is aboard said module.

23. An integrated testing system according to claim 19, comprising a plurality of measurement engines each operatively configured to provide at least one stimulus signal to the circuitry and to generate measurement data that is a function of at least one response of the circuitry to said at least one stimulus signal.

24. An integrated testing system according to claim 23, wherein said compute engine is operatively configured to permit a user to select which one or more of said plurality of measurement engines to use during testing.

25. An integrated testing system according to claim 19, wherein said at least one measurement engine comprises a plurality of stimulus instruments.

26. An integrated testing system according to claim 25, wherein said compute engine is operatively configured to permit a user to select which one or more of said plurality of stimulus instruments to use during testing.

27. An integrated testing system according to claim 19, wherein said at least one measurement engine comprises a plurality of measurement instruments.

28. An integrated testing system according to claim 27, wherein said compute engine is operatively configured to permit a user to select which one or more of said plurality of stimulus measurement instruments to use during testing.

29. An integrated testing system according to claim 19, wherein said compute engine is operatively configured to process said measurement data into a result, said communications engine operatively configured to communicate said result to the at least one device.

30. An integrated testing system according to claim 29, wherein said result is a pass/fail indication.

31. An integrated testing system according to claim 29, wherein the at least one device is a piece of ATE.

32. An integrated testing system according to claim 31, wherein the piece of ATE includes a serial communication link and said communications engine is operatively configured to communicate said results over said serial communications link.

33. An integrated testing system according to claim 29, wherein the device is a host computer containing a non-ATE user interface for the integrated testing system.

34. An integrated testing system according to claim 33, wherein said communications engine includes a high-speed communications link to the non-ATE user interface.

35. An integrated testing system according to claim 19, wherein said communications engine is operatively configured for communicating with both an ATE and a non-ATE user interface.

36. An integrated testing system according to claim 19, further comprising a host computer containing a user interface for controlling the integrated testing system.

37. An integrated testing system according to claim 36, wherein said host computer comprises a network server operatively configured to connect to a network of computers.

38. An integrated testing system according to claim 37, wherein said network server is a Web server.

39. An integrated testing system according to claim 19, wherein at least one of said compute engine and said at least one measurement engine includes at least one RLD and said compute engine is operatively configured to program said at least one RLD via said communications engine.

40. A testing module according to claim 19, wherein said compute engine is operatively configured to generate a plurality of test results substantially in parallel with said at least one measurement engine generating said measurement data.

41. A system for performing a test on a DUT, the system comprising:

a) a testing module that includes;

i) at least one measurement engine operatively configured to provide at least one stimulus signal to the DUT and to generate measurement data that is a function of at least one response of the DUT to said at least one stimulus signal; and

ii) a compute engine in communication with said at least one measurement engine and operatively configured to generate at least one test result as a function of said measurement data; and

b) an interface operatively configured to establish electrical communications between said testing module and the DUT, said interface including;

i) a first socket operatively configured to receive the DUT; and

ii) a second socket receiving said testing module.

42. A system according to claim 41, wherein said interface is an interface board operatively configured to interface with ATE over a communications link.

43. A system according to claim 42, wherein said testing module further comprises a communications engine operatively configured to transmit said at least one test result to the ATE.

44. A system according to claim 42, wherein said communications link is a serial link.

45. A system according to claim 41, wherein said testing module further comprises a communications engine operatively configured to communicate said at least one test result to a non-ATE user interface.

46. A system according to claim 45, wherein said communications engine includes a high-speed communications link to the non-ATE user interface.

47. A system according to claim 41, wherein said compute engine is operatively configured to provide digital data to the DUT when the DUT is engaged with said first socket.

48. A system according to claim 41, wherein said compute engine is operatively configured to generate a plurality of test results substantially in parallel with said at least one measurement engine generating said measurement data.

49. A method of testing circuitry of a DUT, comprising the steps of:

a) engaging a module containing an integrated testing system with an interface;

b) engaging a DUT with said interface; and

c) causing said integrated testing system to conduct a test of circuitry of said DUT.

50. A method according to claim 49, wherein said interface is a device interface board and step c) includes initiating said test via ATE.

51. A method according to claim 50, further comprising the step of setting up said integrated testing system via said ATE.

52. A method according to claim 49, wherein said interface is a device characterization board and step c) includes initiating said test via a non-ATE user interface.

53. A method according to claim 52, further comprising the step of setting up said integrated testing system via said non-ATE user interface.

54. A method according to claim 49, further comprising the step of determining a result of said test aboard said module.

55. A method according to claim 54, further comprising the step of communicating said result off-board of said module.

56. A method according to claim 55, wherein the step of communicating said result off-board of said module comprises communicating said test result to ATE.

57. A method according to claim 56, wherein the step of communicating said result off-board of said module comprises communicating said test result to a non-ATE user interface.

58. A method according to claim 49, wherein said test comprises the steps of providing at least one stimulus signal to said DUT and measuring at least one response signal from said DUT, the method further comprising the step of performing computations on response data substantially simultaneously with the performance of said test.

59. A method according to claim 49, further comprising the step of programming at least one of a PLD and an RLD.

60. A method of programming an integrated testing system, comprising the steps of:

a) engaging an integrated testing system with a device interface board, said integrated testing system being programmable for testing circuitry of a DUT; and

b) downloading instructions from ATE to said integrated testing system via said device interface board.

61. A method according to claim 60, wherein said integrated testing system includes at least one of a PLD and an RLD and step b) includes downloading instructions for programming said at least one of said PLD and said RLD.

62. A method according to claim 60, wherein said integrated testing system requires setting up prior to testing a DUT and step b) includes downloading instruction for setting up said integrated testing system.

63. A method according to claim 60, wherein the ATE includes a data vector communications link and step b) includes downloading instructions via said data vector communications link.

64. A method of testing circuitry of a DUT, comprising the steps of:

a) placing a DUT within about 6 inches (15.24 cm) of a testing module comprising an integrated testing system that includes at least one measurement engine and a compute engine; and

b) causing said integrated testing system to test circuitry aboard the DUT.

65. A method according to claim 64, further comprising the step of communicating a result of said test off-board of said module.

66. A method according to claim 64, wherein step a) includes engaging said DUT with an interface.

67. A method according to claim 66, wherein said interface is an interface board.

68. A method of testing a first plurality of DUTs, comprising the steps in the recited order of:

a) engaging an integrated testing system with an interface;

b) downloading a first testing program to said integrated testing system; and

c) testing each DUT of said first plurality of DUTs in seriatim with one another via said interface.

69. A method according to claim 68, further including testing a second plurality of DUTs, the method further comprising following step c) the steps of downloading a second testing program to said integrated testing system and testing each DUT of said second plurality of DUTs in seriatim with one another via said interface, said second testing program being different from said first testing program.

70. A method according to claim 68, wherein step b) is performed via ATE.

71. A method according to claim 68, wherein step a) includes engaging said integrated testing system with an interface board and step c) includes engaging each DUT of said first plurality of DUTs with said interface board.