Input buffer with automatic switching point adjustment circuitry, and synchronous dram device including same
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Abstract
An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level, where the first and second voltage levels may vary over time. In one embodiment, the input buffer includes a first and second detector circuits, an average generator circuit, and a differential amplifier. The first detector circuit receives the input signal and produces a first signal having a magnitude indicative of the first voltage level. The second detector circuit receives the input signal and produces a second signal having a magnitude indicative of the second voltage level. The average generator circuit receives the first and second signals, and uses the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level. The third voltage level defines a variable an automatically adjusted “switching point”. The differential amplifier receives the input signal, the third signal, and a first and second power supply voltages. The differential amplifier amplifies a difference between the voltage magnitude of the input signal and the third voltage level in order to produce an output signal which alternates between the first and second power supply voltages. An integrated circuit is described including the input buffer coupled between one of a set of input/output pads and circuitry, wherein the circuitry may be synchronous dynamic random access memory (SDRAM) circuitry.
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Citations
80 Claims
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1-54. -54. (canceled)
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55. A semiconductor device, comprising:
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a semiconductor substrate;
a detector circuit formed in or on the semiconductor substrate, the detector circuit being adapted to receive an input signal, wherein a voltage magnitude of the input signal alternates between a first voltage level and a second voltage level, and wherein the detector circuit is configured to produce a first signal having a magnitude indicative of the first voltage level and a second signal having a magnitude indicative of the second voltage level; and
an average generator circuit formed in or on the semiconductor substrate, the average generator circuit being adapted to receive the first and second signals and configured to use the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level. - View Dependent Claims (56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75)
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72-1. The memory device of claim 71, further comprising a differential amplifier coupled to the input/output pad and coupled to receive the third signal, a first power supply voltage, and a second power supply voltage, wherein the differential amplifier is configured to amplify a difference between the voltage magnitude of the input signal and the third voltage level in order to produce an output signal which alternates between the first and second power supply voltages.
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76. A dynamic random access memory device, comprising:
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an input/output pad adapted to receive an input signal, wherein a voltage magnitude of the input signal alternates between a first voltage level and a second voltage level;
an input buffer, comprising;
a first detector circuit coupled to the input/output pad and configured to produce a first signal having a magnitude indicative of the first voltage level of the input signal;
a second detector circuit coupled to the input/output pad and configured to produce a second signal having a magnitude indicative of the second voltage level of the input signal;
an average generator circuit coupled to receive the first and second signals and configured to use the magnitudes of the first and second signals to produce a third signal having a magnitude indicative of a third voltage level substantially mid way between the first voltage level and the second voltage level; and
at least one dynamic random access memory element coupled to receive the third signal and configured to perform a function dependent upon the third signal. - View Dependent Claims (77, 78, 79, 80)
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Specification