Circuit with at least one delay cell

• US 20050253641A1
• Filed: 05/17/2005
• Published: 11/17/2005
• Est. Priority Date: 05/17/2004
• Status: Abandoned Application

• Current Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Karthaus, Udo
• Application Number:
  US11/130,280
• Publication Number:
  US 20050253641A1
• Time in Patent Office: Days
• US Class Current: 327/261
• CPC Class Codes: H03K 3/0322 with differential cells

Abstract

A circuit having at least one delay cell that reflects an input signal change in an output signal with a delay and that has at least two pairs of inverters, wherein the outputs of the inverters of each pair of inverters are connected to one another so that the connected outputs of a first pair of inverters form a first output of the delay cell and the connected outputs of a second pair form a second output. The circuit is characterized in that one input of each inverter is connected to its own input of the delay cell, separately from inputs of other inverters.

Claims

1. A circuit having at least one delay cell that reflects an input signal change in an output signal with a delay, the delay cell includes at least two pairs of inverters, outputs of the inverters of each pair of inverters are connected to one another so that the connected outputs of first connected inverters form a first output of the delay cell and the connected outputs of second connected inverters form a second output,

wherein an input for each inverter is connected to its own respective input of the delay cell, thereby being separate from inputs of the other inverters.

2. The circuit according to claim 1, wherein each of the inverters are CMOS inverters.

3. The circuit according to claim 1, wherein at least one output of the delay cell is connected to an amplifier element.

4. The circuit according to claim 3, wherein the amplifier element is an inverter.

5. The circuit according to claim 1, wherein the circuit has a number N of delay cells that is divisible by two and is greater than or equal to four, wherein inputs of at least one nth delay cell are connected to outputs of at least one n−

1 modulo Nth and one n−

2 modulo Nth delay cell.

6. The circuit according to claim 1, wherein at least four delay cells are connected to one another such that a first signal path through a first chain of inverters and a second signal path through a second chain of inverters is formed, wherein signals in the two signal paths advance synchronously in opposite phase, and wherein inputs of inverters in the first chain, belonging to an nth delay cell, are connected to outputs of inverters of the first chain, belonging to an (n−

2k+/−

1) modulo Nth delay cell and are connected to outputs of inverters of the second chain belonging to an (n−

2kth) modulo N delay cell, where k is a natural number greater than or equal to 1.

7. The circuit according to claim 1, wherein at least four delay cells are connected to one another to thereby form a ring oscillator.

8. The circuit according to claim 1, wherein at least one source of electrical energy is connected to supply connections of at least one of the inverters.

9. The circuit according to claim 8, wherein the source of electrical energy is provided by at least one voltage source and/or current source.

10. The circuit according to claim 9, wherein the at least one current source supplies all of the delay cells with electrical energy.

11. The circuit according to claim 9, wherein each delay cell has its, own respective current source.

12. A delay cell comprising:

a first inverter unit having a first pair of inverters, outputs of the first pair of inverters being connected to one another to thereby provide a first output signal; and

a second inverter unit having a second pair of inverters, outputs of the second pair of inverters being connected to one another to thereby provide a second output signal,

wherein each inverter of the first pair of inverters and the second pair of inverters is provided with an input signal that is different from one another.

13. The delay cell according to claim 12, wherein a plurality of delay cells are connected to one another such that the first inverter unit from a succeeding delay cell receives the second output signal from a preceding delay cell, and such that the second inverter unit from the succeeding delay cell receives the first output signal from the preceding delay cell.

14. A method for delaying an input signal in a circuit, the method comprising the steps of:

providing a first delay cell and a second delay cell, each delay cell having a first inverter unit having a first pair of inverters, outputs of the first pair of inverters being connected to one another to thereby provide a first output signal, a second inverter unit having a second pair of inverters, outputs of the second pair of inverters being connected to one another to thereby provide a second output signal;

connecting the first inverter unit from the second delay cell to receive the second output signal from the first delay cell;

connecting the second inverter unit from the second delay cell to receive the first output signal from the preceding delay cell; and

controlling an input source, which is connected to at least one of the pairs of inverters of the delay cell, to thereby control a delay time of the inverter connected to the input source.