Digital predistortion apparatus and method in power amplifier

• US 20050253652A1
• Filed: 05/11/2005
• Published: 11/17/2005
• Est. Priority Date: 05/11/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Seung-Hwan, Maeng, Seung-Joo, Lee, Jae-Hyok, Jeon, Jae-Ho, Hwang, Ki-Hwan, Song, Yoo-Seung
• Granted Patent: US 7,561,636 B2
• Time in Patent Office: Days
• US Class Current: 330/149
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence

Abstract

A digital predistortion apparatus is provided for predistorting a nonlinear characteristic caused by a wideband power amplifier that amplifies a input signal. The digital predistortion apparatus includes a predistorter, connected to the power amplifier via a digital-to-analog converter (DAC) and a frequency up-converter, for receiving the input signal and compensating for the nonlinear characteristic using a look-up table that depends upon a change in output power of the power amplifier. The digital predistortion apparatus further includes look-up table (LUT) updating block for adaptively updating the look-up table by comparing a feedback signal output from the power amplifier, connected thereto via an analog-to-digital converter (ADC), with the input signal output from the predistorter.

Claims

1. A digital predistortion apparatus for compensating by predistorting a nonlinear characteristic caused by a power amplifier that amplifies a input signal, the apparatus comprising:

a predistorter, electrically connected to the power amplifier via a digital-to-analog converter (DAC), for receiving the input signal and compensating for the nonlinear characteristic using a look-up table that depends upon a change in output power of the power amplifier; and

a look-up table (LUT) updating block, electrically connected to the predistorter, for comparing a feed-back signal from the power amplifier with a output signal from the predistorter, and adaptively updating the look-up table using the compared result.

2. The digital predistortion apparatus of claim 1, wherein the predistorter comprises:

a look-up table converged at a specific power value;

an address decider for calculating an intensity of the input signal and determining an address of the look-up table according to a change in output power of the power amplifier; and

a multiplier for multiplying the input signal by a value read from the look-up table using the determined address.

3. The digital predistortion apparatus of claim 2, wherein the address decider comprises:

a controller including a table in which an output power is matched to a coefficient value for selecting a look-up table corresponding to the output power, wherein the controller is programmable to output a coefficient to which a value for changing the output power is mapped;

squarers for individually squaring a real-part signal and an imaginary-part signal, wherein the real-part signal and the imaginary-part signal are obtained by dividing the input signal;

an adder for adding signals output from the squarers;

a first multiplier for dividing the added signal by an LUT step size; and

a second multiplier for multiplying a signal output from the first multiplier by the coefficient value.

4. The digital predistortion apparatus of claim 1, wherein the LUT updating block comprises:

a delay unit for calculating a time delay between an input signal output from the predistorter and a feedback signal output from the power amplifier, delaying the input signal by the calculated time delay, and providing the delayed input signal to an adaptation controller;

the adaptation controller for updating a polynomial coefficient converged to reduce a difference between an output value and a target value; and

an LUT converter for converting the polynomial coefficient converged in the adaptation controller into a look-up table to update the look-up table.

5. A digital predistortion method for compensating by predistorting a nonlinear characteristic caused by a power amplifier that amplifies a input signal, the method comprising the steps of:

adaptively updating a look-up table by comparing a feedback signal output from the power amplifier, with a input signal output from a digital predistorter; and

receiving the input signal and compensating for the nonlinear characteristic using a look-up table that depends upon a change in an output power of the power amplifier.

6. The digital predistortion method of claim 5, wherein the step of compensating for the nonlinear characteristic comprises the steps of:

calculating an intensity of the input signal;

detecting a coefficient corresponding to a change in output power;

outputting an address by multiplying the intensity of the input signal by the coefficient; and

multiplying the input signal by a value read from the look-up table using the address.

7. A digital predistortion apparatus for compensating by predistorting a nonlinear characteristic caused by a power amplifier that amplifies a input signal, the apparatus comprising:

a predistorter, electrically connected to the power amplifier via a digital-to-analog converter (DAC), for receiving the input signal and compensating for the nonlinear characteristic using a data storage device that depends upon a change in output power of the power amplifier; and

a data storage device updating block, electrically connected to the predistorter, for adaptively updating the data storage device by comparing a feedback signal output from the power amplifier connected thereto via an analog-to-digital converter (ADC), with the input signal output from the predistorter.

8. The digital predistortion apparatus of claim 7, wherein the predistorter comprises:

a data storage device converged at a specific power value;

an address decider for calculating an intensity of the input signal and determining an address of the data storage device according to a change in output power of the power amplifier; and

a multiplier for multiplying the input signal by a value read from the data storage device using the calculated address.

9. The digital predistortion apparatus of claim 8, wherein the address decider comprises:

a controller including a table in which an output power is matched to a coefficient value for selecting a data storage device corresponding to the output power, wherein the controller is programmable to output a coefficient to which a value for changing the output power is mapped;

squarers for individually squaring a real-part signal and an imaginary-part signal, wherein the real-part signal and the imaginary-part signal are obtained by dividing the input signal;

an adder for adding signals output from the squarers;

a first multiplier for dividing the added signal by a step size; and

a second multiplier for multiplying a signal output from the first multiplier by the coefficient value.

10. The digital predistortion apparatus of claim 8, wherein the data storage device updating block comprises:

a delay unit for calculating a time delay between an input signal output from the predistorter and a feedback signal output from the power amplifier, delaying the input signal by the calculated time delay, and providing the delayed input signal to an adaptation controller;

the adaptation controller for updating a polynomial coefficient converged to reduce a difference between an output value and a target value; and

a data storage device converter for converting the polynomial coefficient converged in the adaptation controller to update the data storage device.