Integral wiring harness

• US 20050253822A1
• Filed: 04/27/2005
• Published: 11/17/2005
• Est. Priority Date: 02/02/2000
• Status: Active Grant

• Current Assignee: 3M Innovative Properties Company (3M Company)
• Original Assignee: 3M Innovative Properties Company (3M Company)
• Inventors: Bottari, Frank J., Marble, Andrea C., LaCourse, Michele L.
• Granted Patent: US 7,102,624 B2
• Time in Patent Office: Days
• US Class Current: 345/173
• CPC Class Codes: G06F 3/045 using resistive elements, e.g. a single continuous surface or two parallel surfaces put in contact
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 428/24917 including metal layer
• CPC Class Codes: Y10T 428/24926 including ceramic, glass, porcelain or quartz layer

Abstract

A method of manufacturing a touch panel wherein a glass substrate is coated with a resistive layer; a pattern of conductive edge electrodes and a conductive wire trace pattern are applied to the resistive layer; the conductive edge electrodes are electrically isolated from the conductive wire traces; and a protective insulative border layer is applied over the edge electrodes and the wire traces. A touch panel which includes a glass substrate coated with a resistive layer on one surface thereof; a pattern of edge electrodes on the resistive layer; a wire trace pattern on the resistive layer; a trench in the resistive layer between the wire trace pattern and the edge electrode pattern; and a protective insulative border layer over the edge electrode pattern and the wire traces.

Claims

1-18. -18. (canceled)

19. A touch panel comprising:

a resistive layer disposed on a surface of a substrate;

a pattern of edge electrodes disposed on the resistive layer in a border area around the substrate periphery;

wire traces disposed on the resistive layer in the border area, the edge electrodes and wire traces separated by trenches in the resistive layer; and

an insulative material disposed at least in the trenches.

20. The touch panel of claim 19, wherein the resistive layer comprises doped tin oxide.

21. The touch panel of claim 19, wherein the border area is no more than about ⅜

inches wide.

22. The touch panel of claim 19, wherein the insulative material covers the wire traces.

23. The touch panel of claim 19, wherein the insulative material covers the edge electrodes.

24. The touch panel of claim 19, further comprising a hardcoat covering the resistive layer.

25. The touch panel of claim 24, further comprising an antimicrobial coating covering the hardcoat.

26. The touch panel of claim 24, further comprising a scratch resistant coating covering the hardcoat.

27-31. -31. (canceled)