Method of inducing stresses in the channel region of a transistor

• US 20050255667A1
• Filed: 05/14/2004
• Published: 11/17/2005
• Est. Priority Date: 05/14/2004
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Venkataraman, Shankar, Arghavani, Reza, Ingle, Nitin K., Yuan, Zheng, Yieh, Ellie Y.
• Granted Patent: US 7,528,051 B2
• Time in Patent Office: Days
• US Class Current: 438/405
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A method of fabricating a semiconductor device, where the method includes forming on a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a transistor on a substrate, wherein the transistor comprises a channel region configured to conduct charge between a source region and a drain region;

forming a trench adjacent to the transistor;

depositing a material on the substrate and within the trench; and

annealing the material, wherein the material is tensile following the annealing and creates a tensile stress in the channel region, wherein the tensile stress in the channel region is about 800 MPa or more.

3. The method of claim 1, wherein the tensile stress in the channel region is about 1.2 GPa or more.

4. The method of claim 1, wherein the tensile stress in the channel region is about 1.5 GPa or more.

5. The method of claim 1, wherein, following the annealing, the material at a top end of the trench has less tensile stress than the material at a bottom end of the trench.

6. The method of claim 4, wherein the tensile stress in the channel region created by the material in the trench comprises a latitudinal stress component and a longitudinal stress component orthogonal to the latitudinal stress component.

7. The method of claim 5, wherein the longitudinal stress component is substantially collinear with a depth dimension for the trench.

8. The method of claim 1, wherein the trench has a width of about 120 nm or less.

9. The method of claim 1, wherein the trench has a width of about 90 nm or less.

10. The method of claim 1, wherein the trench has a depth to width aspect ratio of about 6:

1 or more.

11. The method of claim 1, wherein the channel region is about 90 nm wide or less between the source region and the drain region.

12. The method of claim 1, wherein the depositing of the material within the trench comprises flowing tetraethoxy silane and ozone into a processing chamber containing the trench.

13. The method of claim 12, wherein a ratio of tetraethoxy silane to ozone flowed into the chamber is increases over time to increase a rate of deposition of the material on the substrate.

14. The method of claim 13, wherein the varying of the ratio of tetraethoxy silane to ozone comprises increasing a flow rate of the tetraethoxy silane relative to a flow rate for the ozone.

15. The method of claim 1, wherein, during the depositing of the material on the substrate, a spacing between the substrate and a gas distribution plate varies over time.

16. The method of claim 15, wherein the spacing is reduced to increase a rate of deposition of the material on the substrate.

17. The method of claim 1, wherein the tensile material is deposited in the trench using sub-atmospheric chemical vapor deposition (SACVD).

2. (canceled)

18. A semiconductor device, comprising:

a transistor comprising a channel region to conduct charge between a source region and a drain region; and

a trench adjacent to the transistor, wherein the trench contains a tensile silicon oxide that creates a tensile stress in the channel region, wherein the tensile stress in the channel region is about 800 MPa or more.

19. The device of claim 18, wherein the tensile stress on the channel region is about 1.2 GPa or more.

20. The device of claim 18, wherein the trench has a width of about 90 nm or less.

21. The device of claim 18, wherein the trench has a depth to width aspect ratio of about 6:

1 or more.

22. The device of claim 18, wherein the silicon oxide at a top end of the trench has less tensile stress than the silicon oxide at a bottom end of the trench.

23. A method of forming a trench isolation in a semiconductor device, the method comprising:

forming a trench in a substrate;

forming a material within the trench at a lower deposition rate;

forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench; and

annealing the material, wherein, after the annealing, the material in the trench is tensile.

24. The method of claim 23, wherein the material formed on the substrate above the trench is compressive after the annealing.

25. The method of claim 23, wherein the material the material in the trench prior to the annealing has a tensile stress of about 200 MPa or more.

26. The method of claim 23, wherein the material the material in the trench after the annealing has a tensile stress of about 800 MPa or more.

27. The method of claim 23, wherein the material comprises silicon oxide.