Delay calculation method, timing analysis method, calculation object network approximation method, and delay control method

• US 20050256921A1
• Filed: 07/15/2004
• Published: 11/17/2005
• Est. Priority Date: 07/16/2003
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Amekawa, Naoki, Ichinomiya, Takahiro, Satoh, Kazuhiro
• Application Number:
  US10/891,496
• Publication Number:
  US 20050256921A1
• Time in Patent Office: Days
• US Class Current: 708/800
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit includes: an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; a coupling capacitance grounding step of multiplying a coupling capacitance by a coefficient obtained from an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and the like, and grounding the value obtained thereby as the coupling capacitance of the delay calculating object net; and a delay value deriving step of deriving the delay value from a circuit obtained by these steps. A problem of the delay calculation method that an accurate delay value cannot be obtained because in actuality, the adjacent wire whose potential fluctuates is approximated to zero potential is solved by this structure.

Claims

1. A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit, said method comprising:

an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; and

a coupling capacitance grounding step of multiplying a coupling capacitance stored between the delay calculation object net and the adjacent net by a coefficient obtained from a delay calculation object net transition, the coupling capacitance, a wire resistance of the adjacent net and a wire capacitance of the adjacent net which are obtained from the delay calculation object net and the adjacent net, and an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and grounding a value obtained thereby as a coupling capacitance of the delay calculating object net,

wherein a delay value is derived from a circuit obtained by these steps.

3. A timing analysis method considering an influence of a delay value by a net adjacent to a net in a timing analysis object path of a semiconductor integrated circuit,

wherein timing verification is performed by using, as a verification condition for a timing verification path, a delay value obtained by the delay calculation method according to claim 1 or 2.

2. A delay calculation method considering a net adjacent to a delay calculation object net of a semiconductor integrated circuit, said method comprising:

an adjacent net internal resistance selecting step of selecting a combination of static state of an adjacent net driving cell; and

a coupling capacitance replacing step of calculating a current that flows through a coupling capacitance obtained from a delay calculation object net transition, a coupling capacitance stored between the delay calculation object net and the adjacent net, a wire resistance of the adjacent net and a wire capacitance of the adjacent net which are obtained from the delay calculation object net and the adjacent net, and an internal resistance of the adjacent net driving cell selected by the adjacent net internal resistance selecting step, and replacing the coupling capacitance and the adjacent net with a current source,

wherein a delay value is derived from a circuit obtained by these steps.

4. A calculation object network approximation method considering a net adjacent to a driven net which is an object of calculation, wherein in accordance with a value of an internal resistance of a driving cell of the adjacent net and a resistance value of a path from the driving cell of the adjacent net to an inter-net capacitance stored between the driven net and the adjacent net, it is determined whether to approximate the inter-net capacitance to connection to ground or to hold a connection of the inter-net capacitance to the adjacent net.

5. A calculation object network approximation method considering a net adjacent to a driven net which is an object of calculation, wherein an inter-net capacitance stored between the driven net and the adjacent net is approximated to connection to ground through a value of an internal resistance of a driving cell of the adjacent net and an equivalent resistance corresponding to a resistance value of a path from the driving cell of the adjacent net to the inter-net capacitance.

6. A calculation object network approximation method considering a net adjacent to a driven net which is an object of calculation, said method comprising:

a step of calculating timing windows between the driven net and the adjacent net; and

a step of, when the timing windows do not overlap, approximating to connection to ground an inter-wire capacitance stored between the driven net and the adjacent net by a capacitance and a resistance of the adjacent net and a value of an internal resistance of a driving cell.

7. A calculation object network approximation method considering a net adjacent to a driven net which is an object of calculation, wherein in accordance with a resistance value of the driven net up to a part constituting an inter-wire capacitance with the adjacent net and a value of the inter-wire capacitance, the inter-wire capacitance is approximated to connection to ground.

8. A delay control method wherein an electrically shielding wire is provided on a driven net which is an object of delay calculation, and the shielding wire is connected to a power source or ground by a high-resistance element.

9. A delay control method wherein an electrically shielding wire is provided on a driven net which is an object of delay calculation, the shielding wire is connected to a power source or ground by a controllable resistance element, and a resistance value in the shielding wire is controlled to thereby control a delay value of the driven net.

10. A delay control method wherein an electrically shielding wire is provided on a driven net which is an object of delay calculation, the shielding wire is connected to a power source or ground by a controllable resistance element, after an LSI is manufactured, operation verification is performed and a wire whose delay varies due to a variation in process is extracted, and a resistance value in the shielding wire is controlled to thereby control a varying delay value of the driven net.

11. A delay control method wherein an electrically shielding wire is provided on a driven net which is an object of delay calculation, the shielding wire is connected to a power source or ground by a controllable resistance element, an influence on a wire delay of the driven net is calculated from a delay time fluctuation detected by an apparatus that detects a delay time fluctuation at a given point in an LSI, and a resistance value in the shielding wire is controlled so that the wire delay fluctuation of the driven net is suppressed.

12. A delay control method wherein a delay fluctuation due to a temperature change of a shielded net is calculated, a capacitance stored between a shielded wire and a shielding wire that suppresses the delay fluctuation due to the temperature change of a driving cell of the shielded net and a resistance value of an element connecting the shielding wire to a power source or ground are calculated, an electrically shielding wire constituting the calculated inter-wire capacitance is provided on the shielded wire, and the shielding wire is connected to the power source or ground by the element of the calculated resistance value.

13. A delay control method wherein a plurality of elements that drive a wire adjacent to a driven net which is an object of delay calculation is connected, switching is made between an element when the adjacent wire is driven and an element when the adjacent wire is not driven, and an internal resistance of a driving cell of the adjacent wire is varied to thereby control a delay value of the driven net.