System and method for communicating the synchronization status of memory modules during initialization of the memory modules
First Claim
1. A method of operating a memory system having a memory hub controller coupled to a plurality of memory hubs each of which includes at least one receiver that is initialized before use, the method comprising:
- transmitting a downstream initialization complete signal from the memory hub controller to one of the memory hubs when initialization of a receiver in the memory hub controller has been completed;
determining if a respective downstream initialization complete signal is being received by each of the memory hubs;
determining if initialization of at least one receiver in each of the memory hubs has been completed;
if the respective downstream initialization complete signal is being received by each of the memory hubs except for a final memory hub furthest downstream from the memory hub controller and initialization of at least one receiver in the memory hub has been completed, transmitting a downstream initialization complete signal from the memory hub;
if the respective downstream initialization complete signal is being received by the final memory hub and initialization of at least one receiver in the final memory hub has been completed, transmitting an upstream initialization complete signal from the memory hub;
if the respective upstream initialization complete signal is being received by each of the memory hubs determining if an upstream initialization complete signal is being received by the memory hub;
if the respective upstream initialization complete signal is being received by each of the memory hubs and initialization of all receivers in the memory hub has been completed, transmitting an upstream initialization complete signal from the memory hub; and
if a respective upstream initialization complete signal is being received by the memory hub controller, transitioning the memory system to normal operation.
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Accused Products
Abstract
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the memory hubs each include at least one receiver that is synchronized to an internal clock signal during initialization. The memory hub controller and the memory hubs each transmit an initialization complete signal downstream when at least one receiver in the controller or hub is initialized and, in the case of the memory hubs, when a downstream initialization signal has also been received. Similarly, the memory hubs transmit an initialization signal upstream to another memory hub or the controller when both of its receivers are initialized and an upstream initialization signal has also been received. Receipt of an upstream initialization signal by the memory hub controller signifies that all of the receivers have been initialized.
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Citations
73 Claims
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1. A method of operating a memory system having a memory hub controller coupled to a plurality of memory hubs each of which includes at least one receiver that is initialized before use, the method comprising:
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transmitting a downstream initialization complete signal from the memory hub controller to one of the memory hubs when initialization of a receiver in the memory hub controller has been completed;
determining if a respective downstream initialization complete signal is being received by each of the memory hubs;
determining if initialization of at least one receiver in each of the memory hubs has been completed;
if the respective downstream initialization complete signal is being received by each of the memory hubs except for a final memory hub furthest downstream from the memory hub controller and initialization of at least one receiver in the memory hub has been completed, transmitting a downstream initialization complete signal from the memory hub;
if the respective downstream initialization complete signal is being received by the final memory hub and initialization of at least one receiver in the final memory hub has been completed, transmitting an upstream initialization complete signal from the memory hub;
if the respective upstream initialization complete signal is being received by each of the memory hubs determining if an upstream initialization complete signal is being received by the memory hub;
if the respective upstream initialization complete signal is being received by each of the memory hubs and initialization of all receivers in the memory hub has been completed, transmitting an upstream initialization complete signal from the memory hub; and
if a respective upstream initialization complete signal is being received by the memory hub controller, transitioning the memory system to normal operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. In a memory system having at least one memory hub each having a downstream receiver, a downstream transmitter, a downstream receiver and an upstream receiver, and a memory hub controller having a downstream transmitter and an upstream receiver, the memory hub controller having its downstream transmitter coupled to the downstream receiver of a first of the memory hubs and its upstream receiver coupled to the upstream transmitter of the first of the memory hubs, each of the memory hubs hubs having its downstream receiver coupled to the downstream transmitter of an upstream one of the memory modules, its upstream transmitter coupled to the upstream receiver of the upstream one of the memory modules, each of the receivers including an initialization circuit for initializing the respective receiver, a method of determining when all of the receivers have been initialized, comprising:
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in the memory hub controller;
transmitting a downstream initialization complete signal from the downstream transmitter when the initialization of the upstream receiver has been completed;
in each of the memory hubs except for a memory hub furthest downstream from the memory hub controller;
determining if a downstream initialization complete signal is being received by the downstream receiver;
determining if initialization of at least one of the downstream receiver and the upstream receiver has been completed; and
if the downstream initialization complete signal is being received by the downstream receiver and initialization of at least one of the downstream receiver and the upstream receiver has been completed, transmitting a downstream initialization complete signal from the downstream transmitter;
in the memory hub furthest downstream from the memory hub controller;
determining if a downstream initialization complete signal is being received by the downstream receiver;
determining if initialization of at least the downstream receiver has been completed; and
if the downstream initialization complete signal is being received by the downstream receiver and initialization of at least the downstream receiver has been completed, transmitting an upstream initialization complete signal from the upstream transmitter;
in each of the memory hubs except for a memory hub furthest downstream from the memory hub controller;
determining if an upstream initialization complete signal is being received by the upstream receiver; and
if the upstream initialization complete signal is being received by the upstream receiver and initialization of both the downstream receiver and the upstream receiver has been completed, transmitting an upstream initialization complete signal from the upstream transmitter; and
in the memory hub controller;
determining if an upstream initialization complete signal is being received by the upstream receiver; and
if the upstream initialization complete signal is being received by the upstream receiver, determining that all of the receivers in the memory hub controllers and all of the memory hubs have been initialized. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method of operation a memory hub controller including a transmitter and an receiver having an initialization circuit for initializing the receiver, the method comprising:
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transmitting an initialization complete signal from the transmitter when the initialization of the receiver has been completed;
determining if the initialization complete signal is being received by the receiver; and
if the initialization complete signal is being received by the receiver, transitioning the memory hub controller to a normal operating mode. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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31. A method of operation a memory hub including an upstream transmitter, a downstream transmitter, an upstream receiver, and a downstream receiver, the method comprising:
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determining if a downstream initialization complete signal is being received by the downstream receiver;
determining if initialization of at least one of the downstream receiver and the upstream receiver has been completed;
if the downstream initialization complete signal is being received by the downstream receiver and initialization of at least one of the downstream receiver and the upstream receiver has been completed, transmitting a downstream initialization complete signal from the downstream transmitter;
determining if an upstream initialization complete signal is being received by the upstream receiver; and
if the upstream initialization complete signal is being received by the upstream receiver and initialization of both the downstream receiver and the upstream receiver has been completed, transmitting an upstream initialization complete signal from the upstream transmitter. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39)
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40. A memory system, comprising:
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a memory hub controller, comprising;
an upstream receiver including an initialization circuit for initializing the receiver, the upstream receiver being operable to determine if an upstream initialization complete signal is being received by the upstream receiver; and
a downstream transmitter transmitting a downstream initialization complete signal when the initialization of the upstream receiver has been completed;
a terminating memory module, comprising;
a plurality of memory devices; and
a memory hub coupled to the plurality of memory devices, the memory hub comprising;
a downstream receiver including an initialization circuit for initializing the receiver, the downstream receiver being operable to determine if a downstream initialization complete signal is being received by the downstream receiver, the downstream receiver further being operable to determine if initialization of the downstream receiver has been completed; and
an upstream transmitter transmitting an upstream initialization complete signal from the upstream transmitter if the downstream initialization complete signal is being received by the downstream receiver and initialization of at least the downstream receiver has been completed; and
at least one intermediate memory module, each intermediate memory module comprising;
a plurality of memory devices; and
a memory hub coupled to the plurality of memory devices, the memory hub comprising;
a downstream receiver coupled to the downstream transmitter in either the memory hub controller or in the memory hub of another of the intermediate memory modules, the downstream receiver including an initialization circuit for initializing the receiver, the downstream receiver being operable to determine if a downstream initialization complete signal is being received by the downstream receiver, the downstream receiver further being operable to determine if initialization of at least one of the downstream receiver and the upstream receiver has been completed;
a downstream transmitter coupled to the downstream receiver in the memory hub of either the terminating memory module or another of the intermediate memory modules, the downstream transmitter being operable to transmit a downstream initialization complete signal if the downstream initialization complete signal is being received by the downstream receiver and initialization of at least one of the downstream receiver and the upstream receiver has been completed;
an upstream receiver coupled to the upstream transmitter in the memory hub of either the terminating memory module or another of the intermediate memory modules, the upstream receiver including an initialization circuit for initializing the receiver, the upstream receiver being operable to determine if an upstream initialization complete signal is being received by the upstream receiver; and
an upstream transmitter coupled to the upstream receiver in either the memory hub controller or in the memory hub of another of the intermediate memory modules, the upstream transmitter being operable to transmit an upstream initialization complete signal if an upstream initialization complete signal is being received by the upstream receiver and initialization of both the downstream receiver and the upstream receiver has been completed. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A memory module, comprising:
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a plurality of memory devices; and
a memory hub coupled to the plurality of memory devices, the memory hub comprising;
a downstream receiver including an initialization circuit for initializing the receiver, the downstream receiver being operable to determine if a downstream initialization complete signal is being received by the downstream receiver, the downstream receiver further being operable to determine if initialization of the downstream receiver has been completed;
a downstream transmitter coupled to the downstream receiver in the memory hub, the downstream transmitter being operable to transmit a downstream initialization complete signal if the downstream initialization complete signal is being received by the downstream receiver and initialization of the downstream receiver has been completed;
an upstream receiver including an initialization circuit for initializing the receiver, the upstream receiver being operable to determine if an upstream initialization complete signal is being received by the upstream receiver; and
an upstream transmitter coupled to the upstream receiver, the upstream transmitter being operable to transmit an upstream initialization complete signal if an upstream initialization complete signal is being received by the upstream receiver and initialization of both the downstream receiver and the upstream receiver has been completed. - View Dependent Claims (53, 54, 55, 56, 57, 58, 59, 60, 61)
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62. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a peripheral device port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a first upstream data bus;
a first downstream data bus;
a memory hub controller coupled to the processor bus, the memory hub controller comprising;
an upstream receiver including an initialization circuit for initializing the receiver, the upstream receiver being operable to determine if an upstream initialization complete signal is being received by the upstream receiver; and
a downstream transmitter transmitting a downstream initialization complete signal when the initialization of the upstream receiver has been completed;
a terminating memory module, comprising;
a plurality of memory devices; and
a memory hub coupled to the plurality of memory devices, the memory hub comprising;
a downstream receiver including an initialization circuit for initializing the receiver, the downstream receiver being operable to determine if a downstream initialization complete signal is being received by the downstream receiver, the downstream receiver further being operable to determine if initialization of the downstream receiver has been completed; and
an upstream transmitter transmitting an upstream initialization complete signal from the upstream transmitter if the downstream initialization complete signal is being received by the downstream receiver and initialization of at least the downstream receiver has been completed; and
at least one intermediate memory module, each intermediate memory module comprising;
a plurality of memory devices; and
a memory hub coupled to the plurality of memory devices, the memory hub comprising;
a downstream receiver coupled to the downstream transmitter in either the memory hub controller or in the memory hub of another of the intermediate memory modules, the downstream receiver including an initialization circuit for initializing the receiver, the downstream receiver being operable to determine if a downstream initialization complete signal is being received by the downstream receiver, the downstream receiver further being operable to determine if initialization of at least one of the downstream receiver and the upstream receiver has been completed;
a downstream transmitter coupled to the downstream receiver in the memory hub of either the terminating memory module or another of the intermediate memory modules, the downstream transmitter being operable to transmit a downstream initialization complete signal if the downstream initialization complete signal is being received by the downstream receiver and initialization of at least one of the downstream receiver and the upstream receiver has been completed;
an upstream receiver coupled to the upstream transmitter in the memory hub of either the terminating memory module or another of the intermediate memory modules, the upstream receiver including an initialization circuit for initializing the receiver, the upstream receiver being operable to determine if an upstream initialization complete signal is being received by the upstream receiver; and
an upstream transmitter coupled to the upstream receiver in either the memory hub controller or in the memory hub of another of the intermediate memory modules, the upstream transmitter being operable to transmit an upstream initialization complete signal if an upstream initialization complete signal is being received by the upstream receiver and initialization of both the downstream receiver and the upstream receiver has been completed. - View Dependent Claims (63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73)
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Specification