Optimized-incrementing, time-gap defect detection apparatus and method

• US 20050257101A1
• Filed: 06/15/2005
• Published: 11/17/2005
• Est. Priority Date: 10/09/2001
• Status: Active Grant

• Current Assignee: Micro-Star International Corporation Limited (Micro-Star International Co., Ltd.)
• Original Assignee: AFTG-TG LLC
• Inventors: Adams, Phillip M.
• Granted Patent: US 7,472,207 B2
• Time in Patent Office: Days
• US Class Current: 714/48
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user. The length of the delays inserted into a data transfer may be determined dynamically using an iterative search technique to more rapidly converge on time-gap defects. Both bisection and Fibonacci search methods are examples that may be used.

Claims

1. An apparatus for programmatically detecting time-gap defects in a computer system having devices interconnected to one another, the apparatus comprising:

a memory device configured to store data structures comprising executables and operational data;

a processor operably connected to the memory device to process the data structures;

a controller configured to control an exchange of data between the devices; and

the memory device, wherein the data structures further comprise a detection module, executable by the processor and comprising;

an operation module configured to initiate an exchange of data between at least two of the devices;

an interrupt module configured to interrupt the exchange of data and insert a delay time having a value dynamically calculated according to a numerical search method; and

a verification module configured to determine whether an error occurred in the exchange and remained undetected to the computer system.

2. The apparatus of claim 1, wherein the numerical search method is the bisection method.

3. The apparatus of claim 2, wherein the detection module further comprises an initialization module configured to initialize variables, internal to the detection module, with the operating parameters.

4. The apparatus of claim 3, wherein the operating parameters are selected from the group consisting of a maximum delay time value, a delay step value, a minimum delay step value, and an initial delay time value.

5. The apparatus of claim 4, wherein the interrupt module is further configured to iteratively insert a delay time equal to the average of the maximum delay time value and the initial delay time value.

6. The apparatus of claim 5, wherein the verification module is further configured to iteratively set the maximum delay time value equal to the delay time if the delay time causes a detected error in the exchange, to set the minimum delay time equal to the delay time if the delay time does not cause a detected error in the exchange, and to set the delay time equal to the current average of the maximum delay and minimum delay.

7. The apparatus of claim 6, wherein the verification module is further configured to cease iteration when the difference between the maximum delay time and the initial delay time value is less than or equal to the minimum delay step.

8. The apparatus of claim 1, wherein the numerical search method is the Fibonacci search method.

9. The apparatus of claim 8, wherein the verification module is further configured to iteratively set calculate the minimum delay time, the maximum delay time, and the delay time according to the Fibonacci search method.

10. An article including a computer readable medium configured to store data structures comprising executables and operational data, the data structures comprising:

a controller driver configured to facilitate exchanging of data between devices in a computer system, and to detect errors occurring in the exchanging process;

a detection module, executable to detect errors occurring in, yet undetected by the computer system, due to timing inconsistencies between the devices, the detection module comprising;

an operation module configured to initiate an exchange of data between at least two of the devices;

an interrupt module configured to interrupt the exchange of data and insert a delay time having a value dynamically calculated according to a numerical search method; and

a verification module configured to determine whether an error occurred in the exchange and remained undetected to the computer system.

11. The article of claim 10, wherein the verification module is further configured to detect a discrepancy between a first device and a second device in selection of a timing increment relied upon.

12. A method for programmatically detecting time-gap defects in computer system components, the method comprising:

providing a detection module configured to execute on a processor to initiate, detect, and verify reporting of errors in data exchanges and operations, controlled by controllers, between devices in a computer system, yet remaining undetected to the computer system.

loading the detection module onto a computer system comprising a processor, a memory, devices connected to exchange data with one another, and controllers for controlling the exchange of data therebetween; and

executing the detection module by the processor.

13. The method of claim 12, wherein executing the detection module further comprises:

effectuating an exchange of data between devices in a computer system;

calculating a delay time according to a numerical search method defining a beginning delay and an ending delay;

interrupting the exchange of data by inserting the delay time therein;

checking the data for any errors incurred by the delay time; and

identifying devices incurring errors without detection thereof.

14. The apparatus of claim 13, wherein executing the detection module further comprises reporting, to a user, any errors undetected in the exchange.

15. The method of claim 14, wherein executing the detection module further comprises re-calculating the delay step according to a numerical search method and re-executing the exchange.

16. The method of claim 15, wherein the delay step is re-calculated based on a numerical search method and based on whether the devices in a computer system detected an error caused by the interrupting of the exchange of data.

17. The method of claim 16, wherein re-executing the exchange further comprises assigning a new value to at least one of the beginning delay and the ending delay according to a numerical search method such that the beginning delay and ending delay are closer in value, and wherein the delay step is calculated according to a numerical search method based on the beginning delay, ending delay, and on whether the devices in a computer system detected an error caused by the interrupting of the exchange of data.

18. The method of claim 17, the numerical search method is either a bisection search method or a Fibonacci search method.

19. The method of claim 18, further comprising setting an “

in process”

flag when the exchange begins and resetting the “

in process”

flag when the exchange ends.

20. The method of claim 19, further comprising re-executing the detection module a until the difference in value between beginning delay and ending delay is within a minimum delay step value.