Method and apparatus for bit error rate test

• US 20050257104A1
• Filed: 05/14/2004
• Published: 11/17/2005
• Est. Priority Date: 05/14/2004
• Status: Abandoned Application

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Wood, Reed Glenn Jr.
• Application Number:
  US10/846,469
• Publication Number:
  US 20050257104A1
• Time in Patent Office: Days
• US Class Current: 714/704
• CPC Class Codes: G01R 31/3171 BER [Bit Error Rate] test
• CPC Class Codes: G01R 31/31932 Comparators

Abstract

A method and apparatus for measuring a bit error rate of a system. A sequencer circuit is programmed to recognize at least one predefined invalid bit pattern. An expected bit pattern is stored, and a bit pattern is received from the device. After the sequencer detects a start of data pattern in the incoming signal and while the sequencer circuit recognizes the received bit pattern as valid, the received bit pattern is compared against the expected bit pattern. A bit error rate is computed based on the number of compared bits and the number of error bits, wherein error bits are bit pattern bits that differ from corresponding bits in the expected bit pattern.

Claims

1. A method, comprising:

programming a sequencer circuit to recognize at least one predefined invalid bit pattern;

storing an expected bit pattern;

receiving a bit pattern from the device; and

after a start of data pattern is received by the sequencer and while the sequencer circuit recognizes the received bit pattern as other than invalid,

comparing the received bit pattern against the expected bit pattern;

computing a bit error rate based on the number of compared bits and the number of error bits, wherein error bits are bit pattern bits that differ from corresponding bits in the expected bit pattern.

2. The method as recited in claim 1, further comprising:

programming the sequencer circuit to recognize a test start bit pattern and a test end bit pattern, wherein start of data pattern comprises the test start bit pattern;

transmitting a transmitted bit pattern to the device,

wherein the transmitted bit pattern comprises, the test start bit pattern, a test bit pattern, and the test end bit pattern; and

in response to the transmitted bit pattern, receiving a return bit pattern from the device as a part of the received bit pattern,

wherein the comparing step occurs after test start bit pattern and before test end bit pattern are detected in the return bit pattern and

wherein the comparing step comprises comparing the return bit pattern against the expected bit pattern.

3. The method as recited in claim 2, wherein the expected bit pattern is identical to the test bit pattern.

4. The method as recited in claim 2, wherein the expected bit pattern differs from the test bit pattern.

5. The method as recited in claim 1, wherein the step computing the bit error rate further comprises:

counting number of compared bits;

counting number of error bits; and

dividing the number of error bits by the number of compared bits,

wherein the result of the dividing step is the bit error rate.

6. The method as recited in claim 5, wherein prior to the step computing the bit error rate, the result of the comparing step is masked to remove preselected bit locations from the count of number of compared bits and from the count of number of error bits.

7. The method as recited in claim 1, wherein the sequencer circuit is a component of a logic analyzer.

8. A computer readable memory device embodying a computer program of instructions executable by the computer, the instructions comprising:

programming a sequencer circuit to recognize at least one predefined invalid bit pattern;

storing an expected bit pattern;

receiving a bit pattern from the device; and

after a start of data pattern is received by the sequencer and while the sequencer circuit recognizes the received bit pattern as other than invalid,

comparing the received bit pattern against the expected bit pattern;

computing a bit error rate based on the number of compared bits and the number of error bits, wherein error bits are bit pattern bits that differ from corresponding bits in the expected bit pattern.

9. The computer readable memory device as recited in claim 8, the instructions further comprising:

programming the sequencer circuit to recognize a test start bit pattern and a test end bit pattern, wherein start of data pattern comprises the test start bit pattern;

transmitting a transmitted bit pattern to the device,

wherein the transmitted bit pattern comprises, the test start bit pattern, a test bit pattern, and the test end bit pattern; and

in response to the transmitted bit pattern, receiving a return bit pattern from the device as a part of the received bit pattern,

wherein the comparing step occurs after test start bit pattern and before test end bit pattern are detected in the return bit pattern and

wherein the comparing step comprises comparing the return bit pattern against the expected bit pattern.

10. The computer readable memory device as recited in claim 9, wherein the expected bit pattern is identical to the test bit pattern.

11. The computer readable memory device as recited in claim 9, wherein the expected bit pattern differs from the test bit pattern.

12. The computer readable memory device as recited in claim 8, wherein the step computing the bit error rate further comprises:

counting number of compared bits;

counting number of error bits; and

dividing the number of error bits by the number of compared bits,

wherein the result of the dividing step is the bit error rate.

13. The computer readable memory device as recited in claim 12, wherein prior to the step computing the bit error rate, the result of the comparing step is masked to remove preselected bit locations from the count of number of compared bits and from the count of number of error bits.

14. The computer readable memory device as recited in claim 8, wherein the sequencer circuit is a component of a logic analyzer.

15. A test instrument for measuring a bit error rate of a device, comprising:

a sequencer circuit capable of receiving a bit pattern from the device and modifying the received bit pattern by removing bit patterns previously identified to the sequencer as invalid;

a memory capable of storing an expected bit pattern;

a digital comparator having a first input, a second input, and an output,

wherein the first input is connected to an output of the sequencer circuit and is capable of receiving bit pattern as modified by the sequencer,

wherein the second input is connected to the memory and is capable of receiving the stored expected bit pattern, and

wherein the output is capable of receiving result of a comparison of bit pattern applied to the first input with bit pattern applied to the second input; and

a bit error rate calculator with input connected to the output of the digital comparator, wherein the bit error rate calculator has capability of calculating a bit error rate.

16. The test instrument as recited in claim 15, wherein the bit rate calculator comprises:

a compared bit counter connected to the digital comparator circuit and having capability of counting the number of bits in the bit patterns compared by the digital comparator;

an error bit counter connected to the digital comparator circuit and having capability of counting the number of error bits in the bit pattern compared by the digital comparator; and

a division logic circuit having inputs separately connected to outputs of the compared bit counter and the error bit counter, having capability of receiving the number counted by the error bit counter and the number counted by the compared bit counter, and having capability of dividing the number received from the error bit counter by the number received from the compared bit counter.

17. The test instrument as recited in claim 15, further comprising:

a bit mask connected to the output of the digital comparator capable of masking predefined bit locations, wherein input of the bit error rate calculator is connected to output of the bit mask and disconnected from the digital comparator circuit.

18. The test instrument as recited in claim 15, wherein the sequencer circuit is a component of a logic analyzer.