Cyclic redundancy check circuit for use with self-synchronous scramblers
First Claim
1. A circuit for detecting and correcting errors in a bit stream, said circuit comprising:
- a. a plurality of bit circuit elements coupled to receive and store said bit stream, each bit circuit element corresponding to a specific bit in a bit pattern;
b. at least one operation circuit element for performing operations between contents of at least two of said bit circuit elements; and
c. at least two logic gates for determining if said contents of said bit circuit elements match specific bit patterns, at least one of said at least two logic gate receiving inputs from said bit circuit elements;
wherein an output of said circuit causes a state of at least one bit in said bit stream to change it contents of said bit circuit elements match at least one of said plurality of specific bit patterns, and said bit patterns correspond to errors that have occurred in said transmitted data.
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Accused Products
Abstract
The present invention provides a circuit for detecting and correcting errors in a bit stream. The circuit consists of a plurality of circuit elements, a least one operation circuit means, and at least two logic gates. The logic gates receive inputs from the plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. The operation circuit elements perform bitwise operations on the contents of at least two of the circuit elements. The bitwise operations are dictated by a cyclical redundancy check (CRC) polynomial and are used to perform the CRC error detection division operation. At the end of the division process for the data to be checked, each circuit element corresponds to a bit in a bit error pattern syndrome and the logic gates determine if the contents of the circuit elements match specific bit error patterns. The circuit causes the state of at least one bit in the bit stream to change if the contents of the plurality of circuit elements match one of the specific bit patterns. The circuit is advantageous in that it may detect single bit errors, and double bit errors that may be caused by error duplication characteristic of a scrambler.
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Citations
14 Claims
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1. A circuit for detecting and correcting errors in a bit stream, said circuit comprising:
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a. a plurality of bit circuit elements coupled to receive and store said bit stream, each bit circuit element corresponding to a specific bit in a bit pattern;
b. at least one operation circuit element for performing operations between contents of at least two of said bit circuit elements; and
c. at least two logic gates for determining if said contents of said bit circuit elements match specific bit patterns, at least one of said at least two logic gate receiving inputs from said bit circuit elements;
wherein an output of said circuit causes a state of at least one bit in said bit stream to change it contents of said bit circuit elements match at least one of said plurality of specific bit patterns, and said bit patterns correspond to errors that have occurred in said transmitted data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A circuit for detecting errors in a bit stream, said circuit comprising:
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operation means for performing bitwise operations between at least a portion of said bit stream and a bit pattern derived from said bit stream; and
detection means for detecting if a bitwise operation between at least a portion of said bit stream and said bit pattern derived from said bit stream produces a result indicating at least one error in said bit stream;
wherein said operation means implements a bitwise operation corresponding to
B(x)=Rem(D(x)/G(x))where D(x) is said at least a first portion of said bit stream;
G(x) is a generator polynomial for the purposes of detecting errors; and
B(x) is a remainder of a division operation between D(x) and G(x);
such that said detection means detects when 8(x) does not equal a pre-determined constant value such as 0. - View Dependent Claims (12, 13, 14)
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Specification