Pipelined data relocation and improved chip architectures

• US 20050257120A1
• Filed: 05/13/2004
• Published: 11/17/2005
• Est. Priority Date: 05/13/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Gorobets, Sergey Anatolievich
• Granted Patent: US 7,490,283 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.

Claims

11. A memory system, comprising:

a controller; and

a memory, including

a non-volatile data storage section;

a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and

a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller.

12. The memory system of claim 11, wherein the second data can be operated upon in the controller concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.

13. The memory system of claim 12, wherein the controller includes error correction circuitry and the controller can perform error correction operations upon the second data concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.

14. The memory system of claim 12, wherein the controller can perform data verification operations upon the second data concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.

15. The memory system of claim 11, wherein the exchange the contents is part of a compound command from the controller

16. The memory system of claim 11, wherein said controller includes a plurality of data buffers and wherein the controller can perform a data checking operation on the contents of a first of said data buffers concurrently with transferring data between another of said data buffers and said memory.

17. The memory system of claim 16, wherein said data checking operation is an error detection and correction operation.

18. The memory system of claim 16, wherein said data checking operation is program-verify operation.

19. The memory system of claim 11, further comprising

a third data register connectable to the first data register and the second data register, whereby the memory exchanges the contents of the first data register with the contents of the second data register by temporarily storing the contents of one of the first and second data registers in the third data register.

20. The memory system of claim 11, wherein first data can be transferred to one of said data registers from the non-volatile data storage section concurrently with transferring second data from the other one of said data registers to the non-volatile data storage section.

21. A memory system, comprising:

a controller including a plurality data buffers; and

a memory including a non-volatile data storage section and one or more data registers, wherein the controller can perform a data checking operation on the contents of a first of said data buffers while concurrently transferring data between another of said data buffers and one of said data registers.

1. A memory system, comprising:

a controller; and

a memory, including;

a non-volatile data storage section; and

first and second data registers to temporarily store data, wherein first data can be transferred between either one of the data registers and the controller concurrently with transferring second data between the other one of the data registers and the non-volatile data storage section.

2. The memory system of claim 1, wherein said with transferring second data between the other one of the data registers and the non-volatile data storage section is a transfer to the non-volatile data storage section and the first data can additionally be transferred to said either one of the data registers from the non-volatile data storage section concurrently with the transferring second data.

3. The memory system of claim 2, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller.

4. The memory system of claim 1, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller.

5. The memory system of any of claims 1-4, wherein the second data can be operated upon in the controller concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.

6. The memory system of claim 5, wherein the controller includes error correction circuitry and the controller can perform error correction operations upon the second data concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.

7. The memory system of claim 5, wherein the controller can perform data verification operations upon the second data concurrently with transferring the first data between said one of the data registers and the non-volatile data storage section.

8. The memory system of claim 1, wherein said controller includes a plurality of data buffers and wherein the controller can perform a data checking operation on the contents of a first of said data buffers concurrently with transferring data between another of said data buffers and said memory.

9. The memory system of claim 8, wherein said data checking operation is an error detection and correction operation.

10. The memory system of claim 8, wherein said data checking operation is program-verify operation.

22. The memory system of claim 21, wherein said data checking operation is an error detection and correction operation.

23. The memory system of claim 21, wherein said data checking operation is program-verify operation.

24. The memory system of claim 21, wherein the controller can additionally perform a programming operation from said one of said data registers concurrently with said data checking operation.

24-1. The memory system of claim 21, wherein the memory includes a plurality of said data registers and wherein first data can be transferred to one of said data registers from the non-volatile data storage section concurrently with transferring second data from the other one of said data registers to the non-volatile data storage section.

25. A method of operating a memory system comprising a controller and a memory including first and second data registers and a non-volatile data storage section, the method comprising:

determining one of said data registers for the transfer of data between the controller and the memory;

transferring first data between the memory array and the other of said data registers; and

transferring second data between said determined one of the data registers and the controller, wherein at least a portion of the transferring second data is performed concurrently with said transferring first data.

26. The method of claim 25, wherein said first data is read from the memory into said other of said data registers.

27. The method of claim 25, wherein said first data is programmed from said other of said data registers into the memory.

28. The method of either of claims 25 and 27, wherein said second data is transferred from the controller.

29. The method of either of claims 25-27, wherein said second data is transferred to the controller.

30. The method of claim 29, further comprising, subsequent to transferring the second data to the controller:

checking/correcting the second data by the controller.

31. The method of claim 30, wherein said checking/correcting the second data comprises:

determining the quality of the second data; and

in response to said determining the quality of the second data, correcting the second data,

the method further comprising;

transferring back the corrected second data from the controller to said determined one of the data registers, wherein the checking/correcting and the transferring back the second data is performed concurrently with said transferring first data.

32. A method of operating a memory system comprising a controller and a memory including first and second data registers and a non-volatile data storage section, the method comprising:

loading first data into a first of said data registers from either the data storage section or the controller;

loading second data into the second of said data registers from either the data storage section or the controller; and

swapping the memory the contents of the first and second data registers in response to a command from the controller.

33. The method of claim 32, wherein the first data is loaded from the controller and the second data is loaded from the data storage section, further comprising, subsequent to said swapping:

transferring the second data from first data register to the controller; and

checking/correcting the second data by the controller.

34. The method of claim 33, wherein said checking/correcting the second data comprises:

determining the quality of the second data; and

in response to said determining the quality of the second data, correcting the second data,

the method further comprising;

transferring back the corrected second data from the controller to the first data register; and

programming the first data from the second data register to the data storage section, wherein said checking/correcting the second data and the transferring the second data to and back from the controller is performed concurrently with said programming first data.

35. The method claim of 32, the memory system further comprising a third data register, the swapping the memory the contents of the first and second data registers comprising:

temporarily storing the contents of one of the first and second data registers in the third data register.

36. A method of operating a memory system comprising a controller including first and second data buffers and a memory including a non-volatile data storage section, the method comprising:

performing a data checking operation on first data stored in a first of the data buffers; and

concurrently transferring second data between the second of the of the data buffers and the memory.

37. The method of claim 36, wherein said data checking operation is a error detection and correction operation.

38. The method of claim 36, wherein said data checking operation is a program verify operation.

39. A method of operating a memory system comprising a controller and a memory including one or more data registers and a non-volatile data storage section, the method comprising sequentially performing in a pipelined manner a plurality of program operations, each of said program operations sequentially comprising the sub-operations of:

writing a data set from one of said one or more data registers to the non-volatile data storage section;

reading the data set as written back to one of said one or more data registers;

transferring the data set as written back to the controller; and

verifying by the controller of the set data as written,

wherein the verifying of the data set for one programming operation is performed concurrently with the writing sub-operation of the following programming operation.

40. The method of claim 39, wherein the transferring of the data set for one programming operation is also performed concurrently with the writing sub-operation of the following programming operation.

41. A method of operating a memory system comprising a controller and a memory a plurality of memory chips, each including one or more data registers and a non-volatile data storage section, the method comprising sequentially performing in a pipelined manner a plurality of data relocation operations on two or more of said memory chips, each of said data relocation operations on a given one of the memory chips sequentially comprising the sub-operations of:

reading a data set from the storage section to one of said one or more data registers;

transferring the data set to the controller;

checking/correcting the data set, wherein said checking/correcting the data set includes;

determining the quality of the data set; and

if the quality of the data set is not acceptable, correcting the data set;

if the data set is corrected, transferring the corrected data set back to one of said one or more data registers; and

programming the data back to the storage section,

wherein the checking/correcting of a first data set for one data relocation operation in a first memory chip is performed concurrently with a sub-operation of a second data set for the following data relocation operation in the first memory chip and concurrently with a sub-operation of a first data set for the following data relocation operation in a second memory chip.

42. The method of claim 41, wherein the first data set in the first memory chip and the first data set in the second memory chip are logically related.

43. The method of claim 42, wherein the first data set in the first memory chip and the first data set in the second memory chip are part of the same metablock.

44. The method of claim 41, wherein said sub-operation of the following data relocation operation is the following data relocation operation'"'"'s programming operation.

45. The method of claim 41, wherein the transferring to and from the controller of the data set for said one data relocation operation is also performed concurrently with the programming sub-operation of the following data relocation operation.

46. The method of claim 41, wherein the reading of the data set for said one data relocation operation is also performed concurrently with the programming sub-operation of the following data relocation operation.