Graphical data flow programming environment with first model of computation that includes a structure supporting second model of computation

• US 20050257194A1
• Filed: 06/16/2004
• Published: 11/17/2005
• Est. Priority Date: 05/14/2004
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Rogers, Steven W., Hogan, Kevin, Andrade, Hugo A., Morrow, Gregory O., Limroth, John C.
• Granted Patent: US 7,506,304 B2
• Time in Patent Office: Days
• US Class Current: 717/109
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

System and method for creating a graphical program that uses multiple models of computation (MoC). A first plurality of graphical program elements is assembled in a graphical program in response to first input, where the assembled first plurality of graphical program elements have a first MoC. A structure is displayed in the graphical program indicating use of a second MoC for graphical program elements comprised within the interior of the structure. A second plurality of graphical program elements is assembled within the structure in response to second input, where the assembled second plurality of graphical program elements have the second MoC. The graphical program is executable to perform a function, for example, by executing the assembled first plurality of graphical program elements in accordance with the first model of computation, and executing the assembled second plurality of graphical program elements in accordance with the second model of computation.

Claims

1. A memory medium that stores program instructions for creating a graphical program, wherein the program instructions are executable to perform:

assembling a first plurality of graphical program elements in a graphical program in response to first input, wherein the assembled first plurality of graphical program elements comprise a plurality of interconnected graphical program elements, wherein the assembled first plurality of graphical program elements have a first model of computation, and wherein the first model of computation specifies a homogenous data flow model of computation;

displaying a structure in the graphical program in response to second input, wherein the structure comprises an interior portion, wherein the structure indicates use of a second model of computation for graphical program elements comprised within the interior portion of the structure; and

assembling a second plurality of graphical program elements within the interior portion of the structure in response to third input, wherein the assembled second plurality of graphical program elements comprised within the interior portion of the structure have the second model of computation;

wherein the graphical program is executable to perform a function.

2. The memory medium of claim 1, wherein the program instructions are further executable to perform:

executing the graphical program, wherein said executing comprises;

executing the assembled first plurality of graphical program elements in accordance with the first model of computation; and

executing the assembled second plurality of graphical program elements in accordance with the second model of computation.

3. The memory medium of claim 2, wherein the program instructions are further executable to perform:

converting the assembled second plurality of graphical program elements having the second model of computation into a third plurality of graphical program elements having the first model of computation;

wherein said executing the assembled second plurality of graphical program elements in accordance with the second model of computation comprises executing the third plurality of graphical program elements in accordance with the first model of computation.

4. The memory medium of claim 2, wherein the program instructions are further executable to perform:

converting the assembled first plurality of graphical program elements having the first model of computation into a third plurality of graphical program elements having the second model of computation;

wherein said executing the assembled first plurality of graphical program elements in accordance with the first model of computation comprises executing the third plurality of graphical program elements in accordance with the second model of computation.

5. The memory medium of claim 1, wherein the first model of computation specifies a single rate execution of graphical program elements.

6. The memory medium of claim 1, wherein the first model of computation does not include explicit feedback connections to implement looping.

7. The memory medium of claim 1, wherein the first model of computation enables specification of parallelism of graphical program elements.

8. The memory medium of claim 1,

wherein the first model of computation specifies a single rate execution of graphical program elements;

and

wherein the first model of computation does not include explicit feedback connections to implement looping.

9. The memory medium of claim 1, wherein the first model of computation comprises graphical structure nodes that specify looping, wherein the graphical structure nodes do not include explicit feedback connections to implement looping.

10. The memory medium of claim 1, wherein the first model of computation comprises graphical structure nodes that specify conditional branching of operations.

11. The memory medium of claim 1, wherein the first model of computation comprises graphical structure nodes that specify sequencing of operations.

12. The memory medium of claim 1,

wherein the graphical program comprises a data flow diagram;

wherein the first model of computation comprises a first data flow semantics; and

wherein the second model of computation comprises a second data flow semantics.

13. The memory medium of claim 1, wherein the first model of computation comprises a basis model of computation operable to implement the second model of computation.

14. The memory medium of claim 1, wherein the second model of computation comprises a basis model of computation operable to implement the first model of computation.

15. The memory medium of claim 1, wherein the second model of computation supports a multi-rate execution of graphical program elements.

16. The memory medium of claim 1, wherein the second model of computation includes explicit feedback connections to implement looping.

17. The memory medium of claim 1,

wherein the second model of computation specifies a multi-rate execution of graphical program elements;

and

wherein the second model of computation includes explicit feedback connections to implement looping.

18. The memory medium of claim 1, wherein the second plurality of graphical program elements comprises a control block diagram utilizing control block notation.

19. The memory medium of claim 1, wherein the second plurality of graphical program elements comprises a simulation diagram, wherein at least a subset of the second plurality of graphical program elements comprise simulation nodes, and wherein the simulation diagram implements a simulation.

20. The memory medium of claim 19, wherein the simulation nodes support direct feed-through and indirect feed-through for inputs and outputs of the simulation nodes.

21. The memory medium of claim 19,

wherein at least one of the simulation nodes comprises a plurality of inputs and a plurality of outputs;

wherein a first output of the plurality of outputs requires only a subset of the plurality of inputs; and

wherein the least one of the simulation nodes is operable to fire upon reception of the subset of the plurality of inputs to generate the first output.

22. The memory medium of claim 19, wherein at least one simulation node of the simulation nodes supports a feedback cycle between an output of the simulation node and an input of the simulation node.

23. The memory medium of claim 22, wherein at least one simulation node of the simulation nodes supports a feedback cycle between an output of the simulation node and an input of the simulation node if:

the input of the simulation node has indirect feed-through to the output of the simulation node.

24. The memory medium of claim 19, wherein at least one of the simulation nodes executes two or more times per execution of the simulation diagram.

25. The memory medium of claim 19, wherein the program instructions are further executable to perform:

computing a feed-through mapping of inputs to outputs for the simulation nodes; and

storing the feed-through mapping.

26. The memory medium of claim 19, wherein the program instructions are further executable to perform:

configuring one or more simulation parameters for the simulation diagram; and

storing the configured one or more simulation parameters;

wherein the configured one or more simulation parameters specify operation of the simulation diagram.

27. The memory medium of claim 19, wherein at least one of the simulation nodes represents a sub-simulation diagram, wherein the sub-simulation diagram comprises two or more additional simulation nodes.

28. The memory medium of claim 27, wherein the program instructions are further executable to perform:

configuring one or more simulation parameters for the sub-simulation diagram; and

storing the configured one or more simulation parameters;

wherein the configured one or more simulation parameters specify operation of the sub-simulation diagram.

29. The memory medium of claim 27, wherein the two or more additional simulation nodes are operable to execute in the simulation diagram in an inlined manner.

30. The memory medium of claim 19, wherein the structure comprises a simulation loop structure enclosing the second plurality of graphical program elements, and wherein the simulation loop is operable to execute the simulation diagram one or more times to advance the simulation one time step.

31. The memory medium of claim 30,

wherein the simulation loop structure comprises a loop iterator terminal and a stop terminal;

wherein the loop iteration terminal is incremented upon the beginning of a time step;

wherein the stop terminal is evaluated at the end of a time step; and

wherein the simulation is operable to stop at a specified stop time or when the evaluation of the stop terminal indicates that the simulation is to stop.

32. The memory medium of claim 30, wherein the simulation loop structure comprises one or more terminals comprising:

an input terminal for inputting one or more simulation parameters;

an error input terminal for inputting error information to the simulation diagram; and

an error output terminal for outputting error information from the simulation diagram.

33. The memory medium of claim 32, wherein the one or more simulation parameters comprises one or more of:

iteration memory medium;

start time;

stop time;

time step for the simulation;

minimum and maximum time step sizes; and

integrator tolerance.

34. The memory medium of claim 19,

wherein the simulation diagram corresponds to a companion diagram in accordance with the first model of computation;

and

wherein executing the simulation diagram comprises executing the companion diagram.

35. The memory medium of claim 1, wherein the program instructions are further executable to perform:

providing debug information for the assembled first plurality of graphical program elements in accordance with the first model of computation; and

providing debug information for the assembled second plurality of graphical program elements in accordance with the second model of computation.

36. The memory medium of claim 1, wherein the program instructions are further executable to perform:

receiving debug input for the assembled first plurality of graphical program elements in accordance with the first model of computation; and

receiving debug input for the assembled second plurality of graphical program elements in accordance with the second model of computation.

37. The memory medium of claim 1, wherein the second model of computation specifies a synchronous data flow (SDF) model of computation.

38. The memory medium of claim 31, wherein the structure comprises a multi-rate loop structure enclosing the second plurality of graphical program elements, and wherein at least two of the second plurality of graphical program elements have different execution rates.

39. The memory medium of claim 38, wherein the second plurality of graphical program elements comprise an SDF diagram.

40. The memory medium of claim 39, wherein the second plurality of graphical program elements comprise SDF nodes interconnected via one or more edges, and wherein each edge specifies a first-in, first-out (FIFO) buffer and a delay.

41. The memory medium of claim 40, wherein each SDF node is specified to consume a respective first number of tokens, and is further specified to produce a respective second number of tokens, and wherein the delay for each edge specifies an initial number of tokens residing on that edge.

42. The memory medium of claim 41, wherein the program instructions are further executable to perform:

computing a repetitions vector for the SDF diagram, wherein the repetitions vector specifies a respective number of times each SDF node should fire to consume all tokens.

43. The memory medium of claim 40, wherein the program instructions are further executable to perform:

computing a valid periodic schedule for the SDF diagram based on the repetitions vector.

44. The memory medium of claim 43, wherein said computing the valid periodic schedule for the SDF diagram is performed at compile time.

45. The memory medium of claim 43, wherein the program instructions are further executable to perform:

optimizing the periodic schedule regarding one or more of;

program memory;

buffer memory;

context switch overhead; and

performance.

46. The memory medium of claim 39, wherein the program instructions are further executable to perform:

configuring one or more parameters for the SDF diagram; and

storing the configured one or more parameters;

wherein the configured one or more parameters specify operation of the SDF diagram.

47. The memory medium of claim 39,

wherein the SDF diagram corresponds to a companion diagram in accordance with the first model of computation;

and

wherein executing the SDF comprises executing the companion diagram.

48. The memory medium of claim 1, wherein the program instructions are further executable to perform:

converting at least a portion of the graphical program into a form suitable for deployment on a programmable hardware element.

49. The memory medium of claim 48, wherein the program instructions are further executable to perform:

deploying the converted at least a portion of the graphical program onto the programmable hardware element; and

executing the graphical program, wherein said executing comprises executing the converted at least a portion of the graphical program on the programmable hardware element.

50. The memory medium of claim 1, wherein the second model of computation specifies one or more of:

cyclostatic data flow; and

parameterized data flow.

51. The memory medium of claim 1,

wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program.

52. The memory medium of claim 1, wherein said including a first plurality of graphical program elements in a graphical program in response to first input comprises:

arranging a plurality of nodes on a display; and

interconnecting the plurality of nodes.

53. The memory medium of claim 1,

wherein the graphical program comprises a block diagram portion and a user interface portion.

54. The memory medium of claim 1,

wherein the graphical program comprises a heterogeneous graphical data flow program.

55. The memory medium of claim 1,

wherein the graphical program is operable to perform one or more of:

an industrial automation function;

a process control function;

a test and measurement function.

56. The memory medium of claim 1, wherein the program instructions are further executable to perform:

executing the graphical program to perform the function.

57. The memory medium of claim 56,

wherein, during execution of the graphical program, the graphical user interface is displayed on a display of a first computer system and the block diagram executes on a second computer system.

58. The memory medium of claim 56, wherein said executing the graphical program comprises highlighting each graphical program element in the graphical program while the graphical program element is executing.

59. A computer-implemented method for creating a graphical program, the method comprising:

assembling a first plurality of graphical program elements in a graphical program in response to first input, wherein the assembled first plurality of graphical program elements comprise a plurality of interconnected graphical program elements, wherein the assembled first plurality of graphical program elements have a first model of computation, and wherein the first model of computation specifies a homogenous data flow model of computation;

displaying a structure in the graphical program in response to second input, wherein the structure comprises an interior portion, wherein the structure indicates use of a second model of computation for graphical program elements comprised within the interior portion of the structure; and

assembling a second plurality of graphical program elements within the interior portion of the structure in response to third input, wherein the assembled second plurality of graphical program elements comprised within the interior portion of the structure have the second model of computation;

wherein the graphical program is executable to perform a function.

60. A system for creating a graphical program, the system comprising:

a processor;

a memory medium, coupled to the processor; and

an input, coupled to the memory medium and the processor, and operable to receive input;

wherein the memory medium stores program instructions implementing a graphical data flow programming environment, wherein the program instructions are executable by the processor to;

assemble a first plurality of graphical program elements in a graphical program in response to first input, wherein the assembled first plurality of graphical program elements comprise a plurality of interconnected graphical program elements, wherein the assembled first plurality of graphical program elements have a first model of computation, and wherein the first model of computation specifies a homogenous data flow model of computation;

display a structure in the graphical program in response to second input, wherein the structure comprises an interior portion, wherein the structure indicates use of a second model of computation for graphical program elements comprised within the interior portion of the structure; and

assemble a second plurality of graphical program elements within the interior portion of the structure in response to third input, wherein the assembled second plurality of graphical program elements comprised within the interior portion of the structure have the second model of computation;

wherein the graphical program is executable to perform a function.

61. A memory medium that stores program instructions for creating a graphical program, wherein the program instructions are executable to perform:

including a first plurality of graphical program elements in a graphical program in response to first input, wherein the included first plurality of graphical program elements comprise a plurality of interconnected graphical program elements, wherein the first plurality of graphical program elements comprise a first portion of the graphical program in accordance with a first model of computation, wherein the first model of computation specifies a homogenous data flow model of computation;

including a structure in the graphical program, wherein the structure comprises an interior portion, wherein the structure indicates a second portion of the graphical program in accordance with a second model of computation for graphical program elements comprised within the interior portion of the structure; and

including a second plurality of graphical program elements within the interior portion of the structure in response to second input, wherein the structure and the second plurality of graphical program elements comprised within the interior portion of the structure comprise the second portion of the graphical program having the second model of computation;

wherein the graphical program is executable to perform a function by;

executing the first portion of the graphical program in accordance with the first model of computation; and

executing the second portion of the graphical program in accordance with the second model of computation.