Semiconductor device and manufacturing method therefor

• US 20050258452A1
• Filed: 04/19/2005
• Published: 11/24/2005
• Est. Priority Date: 05/12/2004
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Sasaki, Satoshi, Kurokawa, Atsushi, Nakajima, Hirokazu, Umemoto, Yasunari, Imamura, Yoshinori, Kusano, Chushiro, Konishi, Satoru, Endo, Tsuneo
• Granted Patent: US 7,511,315 B2
• Time in Patent Office: Days
• US Class Current: 257/197
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Claims

1. A semiconductor device comprising:

a first semiconductor chip including;

(a1) a plurality of heterojunction bipolar transistors, and

(a2) an emitter bump electrode that is connected in common with the emitter electrodes of a plurality of the heterojunction bipolar transistors and is extended in a predetermined direction; and

(b) a wiring substrate over which the first semiconductor chip is mounted,

wherein the emitter bump electrode is connected with a plurality of via holes so formed that the via holes penetrate the wiring substrate.

2. The semiconductor device according to claim 1,

wherein a second semiconductor chip lower in heat dissipation value than the first semiconductor chip is disposed over a surface of the first semiconductor chip opposite a surface that faces toward the wiring substrate when the first semiconductor chip is mounted over the wiring substrate.

3. The semiconductor device according to claim 2,

wherein the first semiconductor chip is formed with compound semiconductor as a main ingredient, and the second semiconductor chip is formed with silicon as a main ingredient.

4. The semiconductor device according to claim 2,

wherein the semiconductor device is a power amplifier module used in a cellular phone.

5. The semiconductor device according to claim 2, comprising:

multistage amplifier circuits that amplify input signals and a control circuit that controls the multistage amplifier circuits,

wherein, of the multistage amplifier circuits, the amplifier circuit in the first stage and the control circuit are formed in the second semiconductor chip, and of the multistage amplifier circuits, the amplifier circuit including the heterojunction bipolar transistor in a last stage are formed in the first semiconductor chip.

6. The semiconductor device according to claim 2, comprising:

three-staged amplifier circuits that amplify input signals and a control circuit that controls the three-staged amplifier circuits,

wherein, of the three-staged amplifier circuits, the amplifier circuit in the first stage and the control circuit are formed in the second semiconductor chip, and of the three-staged amplifier circuits, the amplifier circuits in the second stages and the amplifier circuits including the heterojunction bipolar transistors in the last stages are formed in the first semiconductor chip.

7. The semiconductor device according to claim 2, comprising:

a first circuit that operates with a first frequency and a second circuit that operates with a second frequency.

8. The semiconductor device according to claim 7,

wherein the first circuit and the second circuit include multistage amplifier circuits that amplify input signals respectively inputted to the first circuit and the second circuit, and

wherein the first-stage amplifier circuit in the first circuit and the first-stage amplifier circuit in the second circuit are formed in the second semiconductor chip, and the last-stage amplifier circuit in the first circuit and the last-stage amplifier circuit in the second circuit are formed in the first semiconductor chip.

9. The semiconductor device according to claim 1, wherein the first semiconductor chip comprises:

(a3) a first base wiring connected in common with base electrodes of a plurality of the heterojunction bipolar transistors;

(a4) a first collector wiring connected in common with collector electrodes of a plurality of the heterojunction bipolar transistors; and

(a5) an emitter wiring connected in common with emitter electrodes of a plurality of the heterojunction bipolar transistors, and

wherein the first base wiring and the first collector wiring are formed in a first wiring layer, the emitter wiring is formed in a second wiring layer, and the emitter bump electrode formed on the emitter wiring is formed in a third wiring layer.

10. The semiconductor device according to claim 9, further comprising:

(a6) a second base wiring formed over the first base wiring;

(a7) a base bump electrode formed over the second base wiring;

(a8) a second collector wiring formed over the first collector wiring; and

(a9) a collector bump electrode formed over the second collector wiring,

wherein the second base wiring and the second collector wiring are formed in the second wiring layer, and the base bump electrode and the collector bump electrode are formed in the third wiring layer.

11. The semiconductor device according to claim 1,

wherein the wiring substrate has a wiring that is so formed that connecting faces of a plurality of the via holes are embraced therein and is formed on the surface of the wiring substrate over which the first semiconductor chip is mounted, and

wherein the first semiconductor chip is mounted over the wiring substrate so that a plurality of the emitter bump electrodes are embraced in the wiring.

12. The semiconductor device according to claim 2,

wherein the first semiconductor chip is mounted with a surface with a plurality of the heterojunction bipolar transistors formed therein facing toward the wiring substrate.

13. The semiconductor device according to claim 12,

wherein the via holes in the semiconductor device are formed of metal,

wherein an external wiring for ground level voltage supply is formed over the surface of the wiring substrate opposite the surface over which the first semiconductor chip is mounted, and

wherein the via holes are connected with the external wiring for ground level voltage supply.

14. The semiconductor device according to claim 5,

wherein passive components are mounted over the wiring substrate.

15. The semiconductor device according to claim 2,

wherein the second semiconductor chip and the wiring substrate are electrically connected with each other through wires.

16. A semiconductor device comprising:

a first semiconductor chip including;

(a1) a plurality of heterojunction bipolar transistors, and

(a2) an emitter bump electrode that is connected in common with emitter electrodes of a plurality of the heterojunction bipolar transistors and is extended in a predetermined direction;

(b) a second semiconductor chip lower in heat dissipation value than the first semiconductor chip; and

(c) a wiring substrate over which the first semiconductor chip and the second semiconductor chip are mounted,

wherein the first semiconductor chip is mounted over the wiring substrate so that the emitter bump electrode is connected with a plurality of via holes penetrating the wiring substrate, and the second semiconductor chip is mounted over a surface of the first semiconductor chip opposite a surface that surface toward the wiring substrate when the first semiconductor chip is mounted over the wiring substrate.

17. A semiconductor device comprising:

(a) a wiring substrate having via holes;

(b) a first semiconductor chip in which heterojunction bipolar transistors are formed; and

(c) a second semiconductor chip lower in heat dissipation value than the first semiconductor chip,

wherein the first semiconductor chip is mounted over the wiring substrate so that the first semiconductor chip is connected with the via holes, and the second semiconductor chip is disposed over a surface of the first semiconductor chip opposite a mounting surface of the first semiconductor chip.

18-20. -20. (canceled)