Low-voltage single-layer polysilicon eeprom memory cell
First Claim
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1. A method of fabricating an electronic memory cell comprising:
- producing a first drain dopant region and a first source dopant region in an uppermost side of a semiconducting substrate, the first drain and first source dopant regions being doped to provide donor sites;
producing a second drain dopant region and a second source dopant region in an uppermost side of a semiconducting substrate, the second drain and second source dopant regions being doped to provide acceptor sites;
constructing a shallow trench isolation region substantially between the first drain/first source dopant regions and the second drain/second source dopant regions;
coupling the first drain dopant region to the second drain dopant region to communicate electrically;
fabricating a PMOS transistor from the second drain and second source dopant regions, the PMOS transistor serving as a select transistor in the memory cell, the PMOS transistor being further configured to have an essentially zero voltage drop between the second source and second drain regions when the PMOS transistor is in an activated state;
fabricating an NMOS transistor from the first drain and first source dopant regions, the NMOS transistor configured to serve as a memory transistor in the memory cell.
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Abstract
The present invention is an electronic memory cell and a method for the cell'"'"'s fabrication comprising a first transistor configured to be coupled to a bit line. The first transistor has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell. A second transistor is configured to operate as a memory transistor and is coupled to the first transistor. The second transistor is further configured to be programmable with a voltage about equal to a voltage on the bit line.
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Citations
20 Claims
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1. A method of fabricating an electronic memory cell comprising:
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producing a first drain dopant region and a first source dopant region in an uppermost side of a semiconducting substrate, the first drain and first source dopant regions being doped to provide donor sites;
producing a second drain dopant region and a second source dopant region in an uppermost side of a semiconducting substrate, the second drain and second source dopant regions being doped to provide acceptor sites;
constructing a shallow trench isolation region substantially between the first drain/first source dopant regions and the second drain/second source dopant regions;
coupling the first drain dopant region to the second drain dopant region to communicate electrically;
fabricating a PMOS transistor from the second drain and second source dopant regions, the PMOS transistor serving as a select transistor in the memory cell, the PMOS transistor being further configured to have an essentially zero voltage drop between the second source and second drain regions when the PMOS transistor is in an activated state;
fabricating an NMOS transistor from the first drain and first source dopant regions, the NMOS transistor configured to serve as a memory transistor in the memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An electronic memory cell comprising:
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a first transistor configured to be coupled to a bit line, the first transistor having essentially zero voltage drop when activated and configured to control an operation of the memory cell;
a second transistor configured to operate as a memory transistor and coupled to the first transistor, the second transistor being further configured to be coupled to a word line, the second transistor further configured to be programmable with a voltage about equal to a voltage on the bit line. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of fabricating an electronic memory cell comprising:
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depositing a p-type epitaxial layer on an uppermost side of a semiconducting substrate;
producing a first drain dopant region and a first source dopant region in the epitaxial layer, the first drain and first source dopant regions being doped to provide donor sites;
producing a second drain dopant region and a second source dopant region in the epitaxial layer, the second drain and second source dopant regions being doped to provide acceptor sites;
producing a doped well in the epitaxial layer, the well being doped with donor sites and large enough to surround the second drain dopant region and the second source dopant region;
constructing a shallow trench isolation region substantially between the first drain/first source dopant regions and the second drain/second source dopant regions;
coupling the first drain dopant region to the second drain dopant region to communicate electrically;
fabricating a PMOS transistor from the second drain and second source dopant regions, the PMOS transistor serving as a select transistor in the memory cell, the PMOS transistor being further configured to have an essentially zero voltage drop between the second source and second drain regions when the PMOS transistor is in an activated state;
fabricating an NMOS transistor from the first drain and first source dopant regions, the NMOS transistor configured to serve as a memory transistor in the memory cell, the memory transistor being configured to operate with a programming voltage of about 10 volts. - View Dependent Claims (17, 18, 19)
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20. A method for writing to an electronic programmable memory cell, comprising:
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applying about 10 volts to a source of a select transistor;
applying 0 volts to a gate of the select transistor;
applying 0 volts to a gate of a memory transistor; and
allowing a source terminal of a memory transistor to float.
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Specification