Resistance-reduced semiconductor device and methods for fabricating the same

• US 20050258499A1
• Filed: 07/28/2005
• Published: 11/24/2005
• Est. Priority Date: 03/23/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Ju-Wang, Shieh, Jyu-Horng, Huang, Yi-Chun
• Granted Patent: US 7,256,498 B2
• Time in Patent Office: Days
• US Class Current: 257/382
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.

Claims

1. A resistance-reduced semiconductor device, comprising:

a resistance-reduced transistor, comprising;

a gate stack on a silicon-containing substrate;

a pair of source/drain regions in the silicon-containing substrate, oppositely adjacent to the gate stack; and

a metallized bilayer overlying each source/drain region to thereby reduce a resistance thereof, wherein the metallized bilayer comprises a metal top layer;

a first dielectric layer having a conductive contact, overlying the resistance-reduced transistor; and

a second dielectric layer having a first conductive feature, overlying the first dielectric layer, wherein the first conductive feature and the conductive contact electrically form a conductive pathway down to the top metal layer over one of the source/drain regions.

2. The semiconductor device as claimed in claim 1, further comprising a metal silicide layer disposed between the metal top layer and each source/drain region.

3. The semiconductor device as claimed in claim 2, wherein the metal top layer comprises the same type of metal ion as that of the metal silicide layer.

4. The semiconductor device as claimed in claim 1, wherein the metal top layer comprises refractory metal.

5. The semiconductor device as claimed in claim 2, wherein the metal silicide layer comprises a silicide of a refractory metal.

6. The semiconductor device as claimed in claim 1, further comprising a conductive cap layer overlying a top surface of the first conductive features.

7. The semiconductor device as claimed in claim 1, further comprising a third dielectric layer having a second conductive feature, overlying the second dielectric layer.

8. The semiconductor device as claimed in claim 7, further comprising a conductive cap layer partially overlying the first conductive feature, wherein the conductive cap layer exposes a portion of the top surface of the first conductive feature to thereby contact the second conductive feature directly and the first conductive feature.

9. The semiconductor device as claimed in claim 6, wherein the conductive cap layer comprises a metal or a metal-containing material.

10. The semiconductor device as claimed in claim 8, wherein the conductive cap layer comprises a metal or a metal-containing material.

11. A method of fabricating a resistance-reduced semiconductor device, comprising:

providing a silicon-containing substrate having a gate stack formed thereon and a pair of source/drain regions oppositely formed in each side of the silicon-containing substrate adjacent to the gate stack, wherein the gate stack comprises an exposed silicon gate electrode;

selectively forming a metal silicide layer over the source/drain regions and the exposed silicon gate electrode;

selectively forming a metal layer over each metal silicide layer by electroless plating to respectively reduce resistance of each source/drain region and the exposed silicon gate electrode;

forming a first dielectric layer having a conductive contact therein, overlying the gate stack and the source/drain regions, wherein the conductive contact electrically contact one of the source/drain regions or the silicon gate electrode of the gate stack; and

forming a second dielectric layer having a first conductive feature, overlying the first dielectric layer, wherein the first conductive feature and the conductive contact are electrically connected and forms a conductive pathway down to the top metal layer over one of the source/drain regions or the silicon gate electrode of the gate stack.

12. The method as claimed in claim 11, wherein the metal layer comprises the same type of metal ion as that of the metal silicide layer.

13. The method as claimed in claim 11, wherein the metal layer comprises refractory metal.

14. The method as claimed in claim 11, wherein the metal silicide layer comprises a silicide of refractory metal.

15. The method as claimed in claim 11, wherein selective formation of the metal layer is formed by an electroless plating using an electrolyte comprising at least a reducing agent, a catalyst, a complex agent and metal ions of the metal layer.

16. The method as claimed in claim 15, wherein the catalyst comprises Pd or the metal ions of the metal layer.

17. The method as claimed in claim 15, further comprising selectively forming a conductive cap overlying a top surface of the first conductive feature.

18. The method as claimed in claim 17, wherein the conductive cap layer comprises a metal or a metal-containing material.

19. The method as claimed in claim 11, further comprising forming a third dielectric layer having a second conductive feature, overlying the second dielectric layer.

20. The method as claimed in claim 19, further comprising selectively forming a conductive cap partially overlying a portion of a top surface of the first conductive feature.

21. The method as claimed in claim 20, wherein the conductive cap layer comprises a metal or a metal-containing material.

22. A method of fabricating a resistance-reduced semiconductor device, comprising:

providing a silicon-containing substrate having a gate stack formed thereon and a pair of source/drain regions oppositely formed in each side of the silicon-containing substrate adjacent to the gate stack, wherein the gate stack comprises an exposed silicon gate electrode;

forming a metallized bilayer over the source/drain regions and the exposed silicon gate electrode to respectively reduce resistance of each source/drain region and the exposed silicon gate electrode, wherein the metallize bilayer comprises a metal top layer;

forming a first dielectric layer having a conductive contact therein, overlying the gate stack and the source/drain regions, wherein the conductive contact electrically contact one of the source/drain regions or the silicon gate electrode of the gate stack; and

forming a second dielectric layer having a first conductive feature, overlying the first dielectric layer, wherein the first conductive feature and the conductive contact are electrically connected and forms a conductive pathway down to the top metal layer over one of the source/drain regions or the silicon gate electrode of the gate stack.

23. The method as claimed in claim 22, further comprising a metal silicide layer between the metal top layer and each source/drain region.

24. The method as claimed in claim 23, wherein the metal top layer comprises the same type of metal ion as that of the metal silicide layer.