Microfabricated miniature grids

• US 20050258514A1
• Filed: 05/06/2005
• Published: 11/24/2005
• Est. Priority Date: 05/07/2004
• Status: Active Grant

• Current Assignee: Stillwater Scientific Instruments, Inc., University of Toledo
• Original Assignee: Stillwater Scientific, The University Of Maine
• Inventors: Collins, Scott, LeGore, Lawrence J., Smith, Rosemary, Frederick, Brian G.
• Granted Patent: US 7,358,593 B2
• Time in Patent Office: Days
• US Class Current: 257/619
• CPC Class Codes: H01J 49/0018 Microminiaturised spectrometers, e.g. chip-integrated devices, Micro-Electro-Mechanical Systems [MEMS]
• CPC Class Codes: H01J 49/061 Ion deflecting means, e.g. ion gates
• CPC Class Codes: H01J 9/14 of non-emitting electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A grid structure and method for manufacturing the same. The grid is used for gating a stream of charged particles in certain types of particle measurement instruments, such as ion mobility spectrometers and the like. The methods include various microfabrication techniques for etching and/or depositing grid structure materials on a silicon substrate.

Claims

1. An integrated microfabricated grid for controlling a charged particle stream, the grid formed of a plurality of electrically isolated conductive elements, comprising:

a substrate to serve as a support for said conductive elements at one of an end thereof, or at another support location within the grid;

a hole in the substrate to allow the charged particle stream to pass therethrough; and

the conductive elements lying in a common plane with one another, and formed from a microfabricated, integral layer disposed adjacent the substrate, the conductive elements having at least one dimension of 10 micrometers (um) or less.

2. A grid as in claim 1 wherein the grid further comprises:

a first and second set of electrically isolated, equally spaced conductors that lie in the same plane both sets of conductors also microfabricated on an integral layer insulated from the substrate, the respective sets of conductors to be applied to alternate electrical potentials.

3. A grid as in claim 1, wherein said conductive elements are single crystal.

4. A grid as in claim 1, wherein said conductive elements are a heavily doped semiconductor.

5. A grid as in claim 1 wherein the semiconductor is selected from a group consisting of silicon, germanium, or a compound semiconductor such as Ga As.

6. A grid as in claim 1, where the microfabricated elements are formed with Deep Reactive Ion Etching (DRIE).

7. A grid as in claim 1, where the microfabricated conductive elements layer are formed using photolithography.

8. A grid as in claim 1, wherein the conductive elements and substrate are microfabricated from a silicon on insulator (SOI) wafer, the SOI wafer having a silicon layer formed adjacent to a silicon oxide insulating layer.

9. A grid as in claim 1, wherein the conductive elements are microfabricated using an additive process such as LIGA.

10. A grid as in any of claims 1 through 9 wherein the conductive elements are further comprised of a first and second set of electrically isolated, equally spaced conductors, and the respective set of conductors are applied to alternate potentials by a common bus bar also formed as integrated part on the substrate.

11. A grid as in claim 8 wherein the substrate that provides support for the conductive elements is an oxide coated micromachined silicon wafer.

12. A grid as in claim 1 wherein the conductive elements are supported at the both ends thereof.

13. A grid as in claim 1 wherein the conductive elements are supported at a mid portion.

14. A method of fabricating a micromachined grid for gating a beam of charged particles, comprising the steps of:

a) selecting a multilayered material consisting of a conductive layer bonded to an insulating layer;

b) patterning a photoresist onto the conductive layer to define a set of conductive elements;

c) micromachining the conductive layer to isolate the set of conductive elements;

d) patterning a photoresist onto the insulating layer to define a region where charged particles may pass through the grid; and

e) micromachining the substrate to open a hole through the grid while providing mechanical support to the ends of the conductive elements.

15. A method as in claim 14, wherein the multilayered material is a silicon on insulator wafer.

16. A method as in claim 14, wherein at least one of the micromachining steps is performed using a process selected from deep reactive ion etching (DRIE) and reactive ion etching (RIE).

17. A method as in claim 14, wherein the conductive elements are formed of a metal.

18. A method as in any of claims 14 through 17, wherein the grid is used for gating a an electron particle beam in a time of flight spectrometer.

19. A method as in any of claims 14 through 17, wherein the grid is used for gating an ion particle beam in a time of flight mass spectrometer.

20. A method as in claim 14 wherein the step of patterning a photoresist on the conductive layer further defines a first and a second set of conductive elements to be applied to alternate potentials.

21. A method as in claim 20 wherein the step of patterning a photoresist on the conductive layer further defines one or more bus bars for providing connection to sources of alternate potentials.

22. A method as in claim 14 wherein the grid is arranged as a Bradbury-Nielson gate.

23. A method as in claim 14 wherein the step of micromachining the conductive layer to isolate the set of conductors is a DRIE process.

24. A method as in claim 14 wherein the step of micromachining the conductive layer to isolate the set of conductors is a wet etching process.

25. A method as in claim 14 additionally comprising a further step of electroplating the set of conductive elements.

26. A method as in claim 14 additionally comprising a further step of electroless plating of the set of conductive elements.

27. A method as in claim 14 wherein the step of micromachining to open a hole is selected from one of RIE or wet etching.

28. A method as in claim 14 wherein multiple grids are formed on the same substrate.

29. A method of fabricating a unipotential grid for defining potential gradients in a charged particle optical system, comprising the steps of:

a) patterning a photoresist onto a semiconductive material layer;

b) micromachining the semiconductive material layer to define a width, depth and spacing of a set of conductive elements that comprise the grid

30. A method as in claim 29 additionally comprising the steps of:

c) patterning a photoresist onto an opposite side of the semiconductive material layer to define a hole where charged particles may pass through the grid; and

d) micromachining the opposite side to open a hole through the grid.

31. A method as in claim 29 wherein the width of the conductive elements is less than about 10 micrometers (um).

32. A method as in claim 29 wherein the semiconductive material is a single crystal.

33. A method as in claim 29 wherein at least one of the micromachining steps is performed using DRIE.

34. A method as in claim 29 wherein the conductive elements are disposed along two orthogonal axes and connected to one another.

35. A method as in claim 29 wherein the grid is used to define potential gradients in a reflectron ion mirror.

36. A method for fabricating a micromachined grid for gating a beam of charge particles, comprising the steps of:

a) patterning a photoresist to define areas on the substrate to be used for conductive elements;

b) adding material to the defined areas on the substrate to produce a set of conductive elements that comprise the grid;

c) removing the photo resist material; and

d) micromachining the substrate to open a hole through the grid.

37. A method as in claim 36 wherein the step of micromachining further defines a frame for supporting the ends of the conductive elements.

38. A method as in claim 36 additionally comprising the step of electroplating to further define the conductive elements.

39. A method as in claim 36 wherein the substrate is an insulator.

40. A method as in claim 36 wherein the substrate is a non-insulating material having an insulating layer on which the conductive elements are defined.