Method and system for stacking integrated circuits

• US 20050258528A1
• Filed: 05/24/2004
• Published: 11/24/2005
• Est. Priority Date: 05/24/2004
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Jensen, Ronald J., Spielberger, Richard K.
• Granted Patent: US 7,863,720 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/731 Location prior to the connecting process
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

A method and system for stacking integrated circuits is described. An integrated circuit stack is formed by stacking integrated circuit pairs. The integrated circuit pairs are formed by connecting an active surface of a first integrated circuit to an active surface of a second integrated circuit using flip chip bonding. The first integrated circuit pair is connected to a substrate using an adhesive. The other integrated circuit pairs are stacked sequentially on the first integrated circuit pair using an adhesive. Wire bonding is used to connect the second integrated circuit in each of the integrated circuit pairs to the substrate.

Claims

1. A method for stacking integrated circuits, comprising in combination:

creating a first integrated circuit pair by flip chip bonding a first integrated circuit to a second integrated circuit;

creating a second integrated circuit pair by flip chip bonding a third integrated circuit to a fourth integrated circuit;

attaching the first integrated circuit pair to a substrate;

stacking the second integrated circuit pair on the first integrated circuit pair;

connecting the second integrated circuit to the substrate using wire bonding; and

connecting the fourth integrated circuit to the substrate using wire bonding.

2. The method of claim 1, wherein the first, second, third, and fourth integrated circuits are rectangular and substantially the same size.

3. The method of claim 1, wherein the step of creating the first integrated circuit pair includes rotating the first integrated circuit 90 degrees with respect to the second integrated circuit and positioning active surfaces of the first and second integrated circuits to be facing each other prior to the flip chip bonding.

4. The method of claim 3, wherein the flip chip bonding includes connecting solder bumps on the first integrated circuit to under bump metallization on the second integrated circuit.

5. The method of claim 1, wherein the step of creating the second integrated circuit pair includes rotating the third integrated circuit 90 degrees with respect to the fourth integrated circuit and positioning active surfaces of the third and fourth integrated circuits to be facing each other prior to the flip chip bonding.

6. The method of claim 5, wherein the flip chip bonding includes connecting solder bumps on the third integrated circuit to under bump metallization on the fourth integrated circuit.

7. The method of claim 1, wherein the step of creating the first integrated circuit pair includes removing wire bond pads from the first integrated circuit and positioning active surfaces of the first and second integrated circuits to be facing each other prior to the flip chip bonding.

8. The method of claim 7, wherein the flip chip bonding includes connecting solder bumps on the first integrated circuit to under bump metallization on the second integrated circuit.

9. The method of claim 1, wherein the step of creating the second integrated circuit paired includes removing wire bond pads from the third integrated circuit and positioning active surfaces of the third and fourth integrated circuits to be facing each other prior to the flip chip bonding.

10. The method of claim 9, wherein the flip chip bonding includes connecting solder bumps on the first integrated circuit to under bump metallization on the second integrated circuit.

11. The method of claim 1, wherein the step of attaching the first circuit pair to the substrate includes attaching an inactive surface of the second integrated circuit to the substrate using an adhesive.

12. The method of claim 1, wherein the step of stacking the second integrated circuit pair on the first integrated circuit pair includes attaching an inactive surface of the fourth integrated circuit to an inactive surface of the first integrated circuit using an adhesive.

13. The method of claim 1, wherein the step of connecting the second integrated circuit to the substrate using wire bonding includes attaching bonding wires between the second integrated circuit and the substrate.

14. The method of claim 1, wherein the step of connecting the fourth integrated circuit to the substrate using wire bonding includes attaching bonding wires between the fourth integrated circuit and the substrate.

15. The method of claim 1, further comprising depositing a first redistribution layer on the first integrated circuit and a second redistribution layer on the second integrated circuit, wherein the first and second redistribution layers allow signals needed on the first integrated circuit to be supplied through wire bond pads on the second integrated circuit.

16. The method of claim 1, further comprising depositing a third redistribution layer on the third integrated circuit and a fourth redistribution layer on the fourth integrated circuit, wherein the third and fourth redistribution layers allow signals needed on the third integrated circuit to be supplied through wire bond pads on the fourth integrated circuit.

17. A stacked integrated circuit, comprising in combination:

a substrate;

a first integrated circuit pair including a first integrated circuit and a second integrated circuit, wherein an active surface of the first integrated circuit is attached to an active surface of the second integrated circuit using flip chip bonding, wherein the first integrated circuit pair is stacked on the substrate, and wherein the second integrated circuit is connected to the substrate using wire bonding; and

a second integrated circuit pair including a third integrated circuit and a fourth integrated circuit, wherein an active surface of the third integrated circuit is attached to an active surface of the fourth integrated circuit using flip chip bonding, wherein the second integrated circuit pair is stacked on the first integrated circuit pair, and wherein the fourth integrated circuit is connected to the substrate using wire bonding.

18. The stacked integrated circuit of claim 17, wherein the first, second, third, and fourth integrated circuits are rectangular and substantially the same size.

19. The stacked integrated circuit of claim 17, wherein the first integrated circuit is rotated 90 degrees with respect to the second integrated circuit prior to the flip chip bonding.

20. The stacked integrated circuit of claim 17, wherein the third integrated circuit is rotated 90 degrees with respect to the fourth integrated circuit prior to the flip chip bonding.

21. The stacked integrated circuit of claim 17, wherein wire bond pads are removed from the first integrated circuit prior to the flip chip bonding.

22. The stacked integrated circuit of claim 17, wherein wire bond pads are removed from the third integrated circuit prior to the flip chip bonding.

23. The stacked integrated circuit of claim 17, wherein an adhesive layer is located between an inactive surface of the second integrated circuit and the substrate.

24. The stacked integrated circuit of claim 17, wherein an adhesive layer is located between an inactive surface of the first integrated circuit and an inactive surface of the fourth integrated circuit.

25. The stacked integrated circuit of claim 17, further comprising a first redistribution layer located on the active surface of the first integrated circuit and a second redistribution layer located on the active surface of the second integrated circuit, wherein the first and second redistribution layers allow signals needed on the first integrated circuit to be supplied through wire bond pads on the second integrated circuit.

26. The stacked integrated circuit of claim 17, further comprising a third redistribution layer located on the active surface of the third integrated circuit and a fourth redistribution layer located on the active surface of the fourth integrated circuit, wherein the third and fourth redistribution layers allow signals needed on the third integrated circuit to be supplied through wire bond pads on the fourth integrated circuit.

27. A stacked integrated circuit, comprising in combination:

a substrate;

a first integrated circuit pair including a first integrated circuit and a second integrated circuit, wherein the first integrated circuit is rotated 90 degrees with respect to the second integrated circuit, wherein a first redistribution layer is located on an active surface of the first integrated circuit and a second redistribution layer is located on an active surface of the second integrated circuit, wherein an active surface of the first integrated circuit is attached to an active surface of the second integrated circuit using flip chip bonding, wherein the first and second redistribution layers allow signals needed on the first integrated circuit to be supplied through wire bond pads on the second integrated circuit, wherein the first integrated circuit pair is stacked on the substrate, and wherein the second integrated circuit is connected to the substrate using wire bonding;

a second integrated circuit pair including a third integrated circuit and a fourth integrated circuit, wherein the third integrated circuit is rotated 90 degrees with respect to the fourth integrated circuit, wherein a third redistribution layer is located on an active surface of the third integrated circuit and a fourth redistribution layer is located on an active surface of the fourth integrated circuit, wherein an active surface of the third integrated circuit is attached to an active surface of the fourth integrated circuit using flip chip bonding, wherein the third and fourth redistribution layers allow signals needed on the third integrated circuit to be supplied through wire bond pads on the fourth integrated circuit, wherein the second integrated circuit pair is stacked on the first integrated circuit pair, and wherein the fourth integrated circuit is connected to the substrate using wire bonding;

an adhesive layer located between an inactive surface of the second integrated circuit and the substrate; and

an adhesive layer located between an inactive surface of the first integrated circuit and an inactive surface of the fourth integrated circuit.

28. The stacked integrated circuit of claim 27, wherein the first, second, third, and fourth integrated circuits are rectangular and substantially the same size.

29. A stacked integrated circuit, comprising in combination:

a substrate;

a first integrated circuit pair including a first integrated circuit and a second integrated circuit, wherein wire bond pads are removed from the first integrated circuit, wherein a first redistribution layer is located on an active surface of the first integrated circuit and a second redistribution layer is located on an active surface of the second integrated circuit, wherein the active surface of the first integrated circuit is attached to the active surface of the second integrated circuit using flip chip bonding, wherein the first and second redistribution layers allow signals needed on the first integrated circuit to be supplied through wire bond pads on the second integrated circuit, wherein the first integrated circuit pair is stacked on the substrate, and wherein the second integrated circuit is connected to the substrate using wire bonding;

a second integrated circuit pair including a third integrated circuit and a fourth integrated circuit, wherein wire bond pads are removed from the third integrated circuit, wherein a third redistribution layer is located on an active surface of the third integrated circuit and a fourth redistribution layer is located on an active surface of the fourth integrated circuit, wherein the active surface of the third integrated circuit is attached to the active surface of the fourth integrated circuit using flip chip bonding, wherein the third and fourth redistribution layers allow signals needed on the third integrated circuit to be supplied through wire bond pads on the fourth integrated circuit, wherein the second integrated circuit pair is stacked on the first integrated circuit pair, and wherein the fourth integrated circuit is connected to the substrate using wire bonding;

an adhesive layer located between an inactive surface of the second integrated circuit and the substrate; and

an adhesive layer located between an inactive surface of the first integrated circuit and an inactive surface of the fourth integrated circuit.

30. The stacked integrated circuit of claim 29, wherein the first, second, third, and fourth integrated circuits are rectangular and substantially the same size.