Integrated circuit with breakdown voltage multiplier

• US 20050258866A1
• Filed: 04/14/2005
• Published: 11/24/2005
• Est. Priority Date: 04/15/2004
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Hajimiri, Seyed Ali, Mandegaran, Sam
• Granted Patent: US 7,321,242 B2
• Time in Patent Office: Days
• US Class Current: 326/82
• CPC Class Codes: H03K 19/00307 in bipolar transistor circuits
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

An apparatus and method for driving an output signal in a high speed integrated circuit. The apparatus and methods enable the output voltage swing from the driver to exceed the breakdown voltage of any individual element in the output driver. A high speed driver can utilize one or more transistors in a stacked configuration, such that the breakdown voltage of the entire stacked configuration is based on the number of transistors in the stack. The driver is configured to distribute the output voltage substantially equally among each of the stacked transistors, such that the driver is able to source an output voltage swing that is greater than the breakdown voltage of any individual transistor in the driver.

Claims

1. An integrated circuit device, the device comprising:

an output stage having a device output and a plurality of output transistors in a stacked configuration; and

a signal distributor configured to receive an input signal at an input, generate a plurality of intermediate driver signals based on the input signal, and couple the intermediate driver signals to the output stage such that each output transistor contributes a portion of an output signal and a total output voltage swing exceeds a breakdown voltage of any one of the plurality of output transistors.

2. The device of claim 1, wherein the output stage comprises:

a first transistor having a collector coupled to the device output and a base coupled to a first intermediate driver output from the signal distributor;

a second transistor having a collector coupled to an emitter of the first transistor and a base coupled to a second intermediate driver output from the signal distributor; and

a load resistor coupled to the collector of the first transistor and a DC voltage source.

3. The device of claim 2, wherein the output stage further comprises a third transistor having a collector coupled to an emitter of the second transistor and a base coupled to a third intermediate driver output from the signal distributor.

4. The device of claim 1, wherein the output stage comprises a differential output stage with each of a complementary subset of output transistors in the differential output stage arranged in the stacked configuration.

5. The device of claim 1, wherein the signal distributor is further configured to substantially equalize a delay from the input to the device output for signal paths through each of the plurality of output transistors.

6. The device of claim 1, wherein the signal distributor is further configured to reduce an impedance at each base of the plurality of output transistors to below a predetermined impedance.

7. The device of claim 1, wherein the signal distributor is configured to generate the plurality of intermediate driver signals such that each of the plurality of output transistors contributes a substantially equal portion of the output signal.

8. The device of claim 1, wherein the input signal comprises a signal having a data rate that exceeds 9 Giga symbols per second.

9. The device of claim 1, wherein the signal distributor is further configured to maintain a phase relationship between each of the plurality of intermediate driver signals and an output signal from each of the plurality of output transistors.

10. The device of claim 1, wherein the signal distributor comprises:

at least one level shifter configured to generate a level shifter version of the input signal as a one of the plurality of intermediate driver signals; and

at least one inverter configured to invert at least one of the plurality of intermediate driver signals to maintain a phase relationship with a corresponding output transistor.

11. The device of claim 1, wherein the signal distributor comprises:

a drive transistor having a base coupled to the input and a collector configured to provide a first intermediate driver signal;

a bias resistor having one end coupled to the collector of the drive transistor and an opposite end coupled to a voltage source; and

a level shifter coupled to the input and configured to provide a second intermediate driver signal.

12. The device of claim 11, further comprising a capacitor coupled in parallel with the bias resistor and configured to substantially equalize a delay through a signal path that passes through the drive transistor with a signal path that passes through the level shifter.

13. The device of claim 11, wherein the level shifter comprises at least one emitter follower stage.

14. The device of claim 1, wherein the integrated circuit device comprises an optical modulation driver.

15. The device of claim 1, wherein the plurality of output transistors comprise a plurality of BJT output transistors.

16. The device of claim 1, wherein the plurality of output transistors comprise a plurality of FET output transistors.

17. An integrated circuit device, the device comprising:

a device input configured to receive a signal having a data rate that exceeds 9 Giga symbols per second;

a drive transistor having a base coupled to the device input and configured to generate a first intermediate driver signal at a collector;

a bias resistor configured to couple the collector of the drive transistor to a first voltage source;

a capacitor coupled in parallel with the bias resistor and configured to delay a signal path through the drive transistor;

a level shifter coupled to the device input and configured to generate a level shifted version of the input signal as a second intermediate driver signal;

a first output transistor having a base coupled to the collector of the drive transistor and a collector coupled to a device output and configured to provide an output signal having a voltage swing that exceeds a breakdown voltage of any transistor within the device;

a load resistor configured to couple the collector of the first output transistor to a second voltage source; and

a second output transistor having a base coupled to the level shifter and a collector coupled to an emitter of the first output transistor.

18. A method of producing a drive signal, the method comprising:

receiving an input signal having a data rate that is greater than 5 Giga symbols per second;

level shifting the input signal to produce a plurality of level shifted signals;

generating a plurality of intermediate driver signals from the plurality of level shifted signals;

coupling each of the plurality of intermediate driver signals to a corresponding one of a plurality of output transistors, wherein the plurality of output transistors are arranged in a stacked configuration; and

providing an output signal from the plurality of output transistors, the output signal having a voltage swing that exceeds a breakdown voltage of any one of the plurality of output transistors.

19. The method of claim 18, further comprising substantially equalizing a signal delay through each of the signal paths passing through at least one of the plurality of output transistors.

20. The method of claim 18, wherein level shifting the input signal comprises buffering the input signal through at least one emitter follower stage.

21. The method of claim 18, wherein generating the plurality of intermediate driver signals comprises synchronizing a phase of each of the plurality of driver signals with a phase of a signal at a collector of a corresponding output transistor from the plurality of output transistors.

22. The method of claim 18, wherein coupling each of the plurality of intermediate driver signals to the corresponding one of the plurality of output transistors comprises coupling each of the plurality of intermediate driver signals to a base of the corresponding one of the plurality of output transistors.

23. The method of claim 18, wherein providing the output signal from the plurality of output transistors comprises providing a portion of the output signal from each of the plurality of output transistors.

24. The method of claim 18, wherein providing the output signal from the plurality of output transistors comprises providing a substantially equal portion of the output signal from each of the plurality of output transistors.

25. The method of claim 18, wherein the plurality of level shifted signals includes a substantially zero shifted signal.