Self-calibrating, fast-locking frequency synthesizer

• US 20050258906A1
• Filed: 05/24/2004
• Published: 11/24/2005
• Est. Priority Date: 05/24/2004
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wang, Chao-Shiun, Su, Chih-Chin
• Granted Patent: US 7,042,253 B2
• Time in Patent Office: Days
• US Class Current: 331/10
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A frequency synthesizer for dual-band high frequency RF application. The frequency synthesizer first uses a frequency-locked loop circuit (“FLL”) to achieve self-calibration and frequency-locking, and then uses a phase-locked loop circuit (“PLL”) to achieve phase-locking. During the FLL, the PLL is de-activated by control signals from the digital control and state machine of the FLL. The varactor of the VCO is initially connected to a fixed voltage, thus isolating the varactor from the PLL. The FLL adjusts the VCO'"'"'s capacitor array by varying the five binary control bits from the state machine and digital control, until frequency-locking and self-calibration is achieved. Then, those five binary weighting control bits are also fixed for the VCO. The PLL is then activated to perform a fine-tuning and phase-locking loop, where the varactor of the VCO is controlled by the signal from the charge pump and the low-pass filter.

Claims

1. A frequency synthesizer having an input (“

Vin”

) and at least one output (“

Vout”

) with variable frequency, the output frequency varying as a capacitance within the frequency synthesizer varies, comprising;

a voltage-controlled oscillator (“

VCO”

) integrated with said frequency synthesizer, said VCO generating said output with a variable frequency, said VCO having a discretely variable capacitance selectably controllable by a first control signal and a continuously variable capacitance selectably controllable by a second control signal;

a frequency-locked loop circuit (“

FLL”

) integrated with said frequency synthesizer, said FLL receiving said Vin and generating said first control signal to said VCO, such that the frequency of said Vout approaches the frequency of said Vin;

a phase-locked loop circuit (“

PLL”

), said PLL receiving said Vin and generating said second control signal to said VCO, such that the phase of said Vout approaches the phase of said Vin,

wherein;

said FLL generates a de-activate signal to isolate said PLL from said VCO while said FLL is operational;

said PLL is activated to control said VCO after said FLL'"'"'s operation.

2. The frequency synthesizer of claim 1, wherein said discretely variable capacitance of said VCO comprises a capacitor array, and said continuously variable capacitance of said VCO comprises a varactor.

3. The frequency synthesizer of claim 2, wherein said de-activate signal generated by said FLL also forces said second control signal from said PLL to a fixed voltage (“

VF”

).

4. The frequency synthesizer of claim 3, wherein said FLL comprises:

a frequency detector, said frequency detector detecting a frequency difference between its inputs;

a digital control coupled to said frequency detector;

a state machine coupled to said digital control, said state machine varying said first control signal to said VCO according to said frequency difference, said state machine also generating said de-activate signal while said frequency difference is still greater than a predetermined value.

5. A frequency synthesizer having an input (“

Vin”

) and at least one output (“

Vout”

) with variable frequency, the output frequency varying as a capacitance within the frequency synthesizer varies, comprising;

a VCO, generating said Vout based on a capacitance within said VCO, said VCO comprising a varactor and a capacitor array for varying the capacitance;

a first frequency divider (“

/M”

), receiving said Vin and generating a 1^st lower frequency signal;

a second frequency divider (“

/N”

), receiving said Vout and generating a 2^nd lower frequency signal;

a frequency detector (“

FD”

), receiving said 1^st and 2^nd signals and determining a frequency difference between said 1^st and 2^nd signals, said FD generating a FD detection signal corresponding to said frequency difference;

a digital control and state machine, receiving said FD detection signal from said FD and generating a multi-bit binary control signal and a state control signal, said binary control signal adjusting said capacitor array of said VCO, said state control signal causing a fixed voltage (“

VF”

) to be applied to said varactor of said VCO, until the frequency difference is stabilized;

a phase/frequency detector (“

PFD”

), receiving said 1^st and 2^nd lower frequency signals and generating a PFD detection signal based on a phase difference between said 1^st and 2^nd signals;

a charge pump, receiving said PFD detection signal and generating a CP control signal to control said varactor of said VCO when said state control signal from said digital control and state machine is not applied;

an external low-pass filter coupled to filter said CP control signal.

6. The frequency synthesizer of claim 5, wherein said digital control and state machine is disposed to set the PFD detection signal to a HIGH until the frequency difference is stabilized.

7. A frequency synthesizer having an input (“

Vin”

) and at least one output (“

Vout”

) with variable frequency, the output frequency varying as a capacitance within the frequency synthesizer varies, comprising;

a VCO, said VCO generating said Vout based on a capacitance within said VCO, said VCO comprising a varactor and a capacitor array for varying the capacitance within said VCO;

a first frequency divider, receiving said Vin and generating a frequency-divided Vin;

a second frequency divider, receiving said Vout and generating a frequency-divided Vout;

a calibration circuit, said calibration circuit discretely varying said capacitor array of said VCO based on the frequency difference between said frequency-divided Vout and Vin until the frequency difference is within a predetermined range, said calibration circuit also generating a calibration control signal until the frequency difference is with said range, said calibration control signal also switchably connecting said varactor to a fixed voltage source;

a PLL circuit, said PLL circuit continuously varying said varactor of said VCO based on the phase difference between said frequency-divided Vout and Vin until the phase difference is within a predetermined range, said PLL remaining de-activated by said calibration control signal from said calibration circuit until the frequency difference is within said range and until said calibration control signal disconnecting said varactor from said fixed voltage.

8. The frequency synthesizer of claim 7, wherein said calibration circuit comprises:

frequency detector, receiving said frequency-divided Vin and said Vout and generating a detection signal;

a digital control and state machine, receiving said detection signal and generating said calibration control signal and a multi-bit binary control signal to said capacitor array.

9. The frequency synthesizer of claim 8, wherein said PLL circuit comprises:

a phase/frequency detector, receiving said frequency-divided Vin and Vout and generating a PFD detection signal, representative of the phase difference between said Vin and Vout;

a charge pump, receiving said PFD detection signal and generating a CP signal;

a low-pass filter, filtering said CP signal;

a switch, selectably connected to said fixed voltage source.

10. The frequency synthesizer of claim 9, wherein said varactor is integrated within said VCO.

11. The frequency synthesizer of claim 10, wherein said low-pass filter is external to said PLL.

12. A method of synthesizing a frequency in a communications receiver, said communication receiver having an input (“

Vin”

) and at least one output (“

Vout”

) with variable frequency, the output frequency varying as a capacitance within the frequency synthesizer varies, comprising the steps of;

using a voltage-controlled oscillator (“

VCO”

) integrated with said frequency synthesizer, said VCO generating said output with a variable frequency, said VCO having a discretely variable capacitance selectably controllable by a first control signal and a continuously variable capacitance selectably controllable by a second control signal;

using a frequency-locked loop circuit (“

FLL”

) integrated with said frequency synthesizer, said FLL receiving said Vin and generating said first control signal to said VCO, such that the frequency of said Vout approaches the frequency of said Vin;

using a phase-locked loop circuit (“

PLL”

), said PLL receiving said Vin and generating said second control signal to said VCO, such that the phase of said Vout approaches the phase of said Vin,

wherein;

said step of using an FLL generates a de-activate signal to isolate said PLL from said VCO while said FLL is operational;

said step of using an PLL is activated to control said VCO after said FLL'"'"'s operation.

13. The method of claim 12, wherein said discretely variable capacitance of said VCO comprises a capacitor array, and said continuously variable capacitance of said VCO comprises a varactor.

14. The method of claim 13, wherein said de-activate signal generated by said FLL also forces said second control signal from said PLL to a fixed voltage (“

VF”

).

15. The method of claim 14, wherein said step of using said FLL comprises:

using a frequency detector, said frequency detector detecting a frequency difference between its inputs;

using a digital control coupled to said frequency detector;

using a state machine coupled to said digital control, said state machine varying said first control signal to said VCO according to said frequency difference, said state machine also generating said de-activate signal while said frequency difference is still greater than a predetermined value.

16. A method of synthesizing frequency in a communications receiver, said receiver having an input (“

Vin”

) and at least one output (“

Vout”

) with variable frequency, the output frequency varying as a capacitance within the frequency synthesizer varies, the method comprising the steps of;

generating, using a VCO, said Vout based on a capacitance within said VCO, said VCO comprising a varactor and a capacitor array for varying the capacitance;

dividing said Vin and generating a 1^st lower frequency signal, using a first frequency divider (“

/M”

),;

dividing said Vout and generating a 2^nd lower frequency signal, using a second frequency divider (“

/N”

);

detecting said 1^st and 2^nd signals and determining a frequency difference between said 1^st and 2^nd signals, using a frequency detector (“

FD”

), said FD generating a FD detection signal corresponding to said frequency difference;

receiving said FD detection signal from said FD and generating a multi-bit binary control signal and a state control signal, using a digital control and state machine, said binary control signal adjusting said capacitor array of said VCO, said state control signal causing a fixed voltage (“

VF”

) to be applied to said varactor of said VCO, until the frequency difference is stabilized;

receiving said 1^st and 2^nd lower frequency signals and generating a PFD detection signal, using a phase/frequency detector (“

PFD”

), based on a phase difference between said 1^st and 2^nd signals;

receiving said PFD detection signal and generating a CP control signal to control said varactor of said VCO, using a charge pump, when said state control signal from said digital control and state machine is not applied;

filtering said CP control signal, using an external low-pass filter.

17. The method of claim 16, wherein said step of said digital control and state machine comprises setting the PFD detection signal to a HIGH until the frequency difference is stabilized.