System and method for variable rate multiple access short message communications

• US 20050259723A1
• Filed: 05/24/2004
• Published: 11/24/2005
• Est. Priority Date: 05/24/2004
• Status: Active Grant

• Current Assignee: General Dynamics C4 Systems Incorporated (General Dynamics Corporation)
• Original Assignee: General Dynamics C4 Systems Incorporated (General Dynamics Corporation)
• Inventors: Blanchard, Scott D.
• Granted Patent: US 8,000,377 B2
• Time in Patent Office: Days
• US Class Current: 375/146
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04J 13/102 Combining codes
• CPC Class Codes: H04J 13/12 Generation of orthogonal codes

Abstract

A communication system and receiver is provided that facilitates increased message size in a communication system that supports a large number of transmitters sharing a common frequency band. The communication system facilitates increased message size by incorporating a plurality of transmit bit sets in each burst of data. The additional transmit bit sets are incorporated into a plurality of transmit codes that are generated using at least one additional spreading code that is orthogonal to the base spreading code. The plurality of transmit codes are then combined into one composite message and the composite message is spread again using another scrambling sequence. The final composite spread message is transmitted to the receiver in the appropriate message time slot, resulting in CDM/TDMA burst signal that facilitates increased message size.

Claims

1. A communications system utilizing code division multiple access (CDMA), time division multiple access (TDMA) and code division multiplexing (CDM) techniques for efficiently transmitting bursts of data from a plurality of users at different data rates to one or more receivers within the system, comprising:

a timing reference for generating a precise timing signal and a corresponding precise time reference;

a plurality of transmitters, coupled to the timing reference for providing synchronization between the plurality of transmitters, for transmitting the bursts of data at precise times and time intervals and at a predetermined frequency within a TDMA superframe wherein synchronization between said plurality of transmitters and the one or more receivers is not needed; and

wherein each of the bursts of data includes data interleaved into a plurality of transmit bit sets using an interleaving multiplexer, the interleaved message data spread across a plurality of transmit codes using a plurality of orthogonal spreading codes, combined and spread using a scrambling sequence and modulated with a carrier thereby permitting transmission of the plurality of transmit bit sets for each burst of data within a corresponding TDMA slot within the TDMA superframe.

2. The communication system of claim 1 wherein the plurality of orthogonal spreading codes comprise Walsh codes.

3. The communication system of claim 1 wherein the scrambling sequence comprises a Gold code.

4. The communication system of claim 1 wherein the scrambling sequence comprises a Kasami sequence.

5. The communication system of claim 1 wherein each burst of data includes forward error correction data bits.

6. The communication system of claim 1 wherein each of the bursts of data comprise a first message spread across a first transmit code in the plurality of transmit codes and a second message in other of the plurality of transmit codes.

7. The communication system of claim 1 wherein each of the bursts of data comprise a first message spread across the plurality of transmit codes.

8. The communication system of claim 1 wherein the plurality of transmit bit sets includes a first transmit bit set and other transmit bit sets, the first transmit bit set including:

a predetermined number of header bits for allowing transmitter settling and for reducing spectral splatter;

a predetermined number of preamble bits for improving a probability of reception of message bits; and

a first predetermined number of the message bits; and

a predetermined number of tail bits for allowing transmitter turn-off; and

wherein the other transmit bit sets includes a second predetermined number of message bits.

9. The communication system of claim 8 wherein the second predetermined number of message bits is equal to the first predetermined number of message bits.

10. The communication system of claim 8 wherein the second predetermined number of message bits is equal to at least the first predetermined number of message bits plus the predetermined number of preamble bits.

11. The communication system of claim 8 wherein the second predetermined number of message bits is equal to the first predetermined number of message bits plus the predetermined number of preamble bits plus a predetermined number of fill bits.

12. The communication system of claim 8 wherein the first predetermined number of message bits comprises a first message and wherein the second predetermined number of message bits comprises a second message.

13. The communication system of claim 8 wherein the first predetermined number of message bits and the second predetermined number of message bits comprises a first message.

14. The communication system of claim 8 wherein the preamble bits include:

signature sequence bits for providing good cross correlation properties between different CDMA channels; and

unique word bits for providing good auto correlation properties for each CDMA channel and improving bit synchronization.

15. The communication system of claim 1 wherein the TDMA superframe includes a plurality of TDMA frames, each TDMA frame including a plurality of time slots for transmitting the bursts of data whereby each one of the plurality of transmitters is assigned (i) at least one time slot within the plurality of TDMA frames for specifying a transmit opportunity, (ii) a position for specifying a first frame within the TDMA superframe for further specifying a transmit opportunity, and (iii) an interval for specifying a number of frames between transmission of bursts of data for further specifying a transmit opportunity.

16. A method for transmitting bursts of data in a communications system having a plurality of transmitters a plurality of receivers, the method comprising the steps of:

synchronizing the plurality of transmitters to a common timing reference thereby abating the need to provide synchronization between the plurality of transmitters and the plurality of receivers;

defining a time division multiple access (TDMA) superframe that includes a plurality of TDMA frames whereby each TDMA frame includes a plurality of time slots for transmission by the plurality of transmitters;

assigning each of the plurality of transmitters a time slot within the plurality of TDMA frames for transmission;

transmitting from a transmitter in the plurality of transmitters to at least one of the plurality of receivers with a time slot assigned to the transmitter, wherein the step of transmitting from the transmitter comprises;

interleaving a burst of data into a plurality of transmit bit sets;

spreading the transmit bit sets across a plurality of transmit codes using a plurality of orthogonal spreading codes; and

combining the spread transmit bit sets and spreading the combined spread transmit bit sets using a scrambling sequence.

17. The method of claim 16 wherein the plurality of orthogonal spreading codes comprise Walsh codes.

18. The method of claim 16 wherein the scrambling sequence comprises a Gold code.

19. The method of claim 16 wherein the scrambling sequence comprises a Kasami sequence.

20. The method of claim 16 wherein the burst of data includes forward error correction data bits.

21. The method of claim 16 wherein the burst of data spread comprises a first message spread across a first transmit code in the plurality of transmit codes and a second message in other of the plurality of transmit codes.

22. The method of claim 16 wherein the burst of data comprises a first message spread across the plurality of transmit codes.

23. The method of claim 16 wherein the plurality of transmit bit sets includes a first transmit bit set and other transmit bit sets, the first transmit bit set including:

a predetermined number of header bits for allowing transmitter settling and for reducing spectral splatter;

a predetermined number of preamble bits for improving a probability of reception of message bits; and

a first predetermined number of the message bits; and

a predetermined number of tail bits for allowing transmitter turn-off; and

wherein the other transmit bit sets include a second predetermined number of message bits.

24. The method of claim 23 wherein the second predetermined number of message bits is equal to the first predetermined number of message bits.

25. The method of claim 23 wherein the second predetermined number of message bits is equal to at least the first predetermined number of message bits plus the predetermined number of preamble bits.

26. The method of claim 23 wherein the second predetermined number of message bits is equal to the first predetermined number of message bits plus the predetermined number of preamble bits plus a predetermined number of fill bits.

27. The method of claim 23 wherein the first predetermined number of message bits comprises a first message and wherein the second predetermined number of message bits comprises a second message.

28. The method of claim 23 wherein the first predetermined number of message bits and the second predetermined number of message bits comprises a first message.

29. The method of claim 23 wherein the preamble bits include:

signature sequence bits for providing good cross correlation properties between different CDMA channels; and

unique word bits for providing good auto correlation properties for each CDMA channel and improving bit synchronization.

30. The method of claim 16 wherein the step of assigning each of the plurality of transmitters a time slot within the plurality of TDMA frames comprises assigning a position for specifying a first frame within the TDMA superframe for transmission, and assigning an interval for specifying a number of frames between successive transmissions of the bursts of data.

31. A receiver for detecting and demodulating a digital message, the receiver comprising:

a despreader responsive to an input signal, the despreader generating a plurality of despread signals, each of the despread signals corresponding to one of a plurality of orthogonal spreading codes;

a plurality of demodulators for demodulating the plurality of despread signals, each of the plurality of demodulator corresponding to one of the plurality of orthogonal spreading codes, each of the plurality of demodulators generating a decision having a value representing the signal quality of its respective despread signal;

a selector, coupled to the plurality of demodulators, for processing the plurality of decisions to generate a message indicator signal when the digital message is detected; and

a plurality of decision blocks, each of the plurality of decision blocks corresponding to one of the plurality of demodulators, each of the plurality of decision blocks comparing a corresponding decision signal to a predetermined value to determine the bit value of the digital message.

32. The receiver of claim 31 wherein the digital message comprises a burst of data interleaved into a plurality of transmit bits and spread across a plurality of transmit codes, combined and spreading using a scrambling sequence and transmitted in a time slot within a TDMA superframe.

33. The receiver of claim 31 wherein the despreader receiver comprises a multi-code multi-channel despreader.

34. The receiver of claim 31 each of the plurality of despread signals further corresponds to one of a plurality of timing channels.

35. The receiver of claim 34 wherein the plurality of demodulators comprise a plurality of demodulator banks, wherein each of the plurality of demodulator banks corresponds to one of the plurality of orthogonal spreading codes, and wherein each of the plurality of demodulator banks includes a plurality of demodulators, each of the plurality of demodulators in each of the plurality of demodulator banks corresponding to one of the plurality of timing channels.

36. The receiver of claim 35 wherein the selector further generates a plurality of signal weights corresponding to each of the plurality of decisions and wherein the receiver further comprises a plurality of multiplier banks, each of the plurality of multiplier banks coupled to a corresponding one of the plurality of demodulator banks, each of the plurality of multiplier banks including a plurality of multipliers, each of the plurality of multipliers in each of the plurality of demodulator banks corresponding to one of the plurality of timing channels, each of the plurality of multipliers multiplying the plurality of decisions by the plurality of signal weights, respectively, to generate a plurality of scaled signals.

37. The receiver of claim 36 further comprising a plurality of combiners, each of the plurality of combiners coupled to a corresponding one of the plurality of multiplier banks, each of the plurality of combiners summing a corresponding plurality of scaled signals to generate a summed scaled signal, and wherein the plurality of decision blocks each compares a corresponding summed scaled signal to a predetermined value to determine the bit value of the digital message.

38. The receiver of claim 31 wherein the selector receives a plurality of decisions only from a first demodulator in the plurality of demodulator.

39. The receiver of claim 31 further comprising a first message extractor for extracting a first message from the digital message.

40. The receiver of claim 39 further comprising a second message extractor for extracting a second message from the digital message.

41. The receiver of claim 31 wherein each of the plurality of demodulators is a noncoherent BPSK demodulator for computing the dot product of its respective one of the plurality of despread signals with itself delayed by one bit period.

42. A receiver for detecting and demodulating a digital message, the receiver comprising:

a despreader responsive to an input signal, the despreader generating a plurality of despread signals, each of the despread signals corresponding to one of a plurality of orthogonal spreading codes and to one of a plurality of timing channels;

a plurality of demodulator banks for demodulating the plurality of despread signals, each of the plurality of demodulator banks corresponding to one of the plurality of orthogonal spreading codes, each of the plurality of demodulator banks including a plurality of demodulators, each of the plurality of demodulators in each of the plurality of demodulator banks corresponding to one of the plurality of timing channels, each of the plurality of demodulators in each of the plurality of demodulator banks generating a decision having a value representing the signal quality of its respective despread signal;

a selector, coupled to the plurality of demodulator banks, for processing the plurality of decisions to generate a message indicator signal when the digital message is detected and for generating a plurality of signal weights corresponding to each of the plurality of decisions;

a plurality of multiplier banks, each of the plurality of multiplier banks coupled to a corresponding one of the plurality of demodulator banks, each of the plurality of multiplier banks including a plurality of multipliers for multiplying the plurality of decisions by the plurality of signal weights, respectively, to generate a plurality of scaled signals;

a plurality of combiners, each of the plurality of combiners coupled to a corresponding one of the plurality of multiplier banks, each of the plurality of combiners summing a corresponding plurality of scaled signals to generate a summed signal; and

a plurality of decision blocks, each of the plurality of decision blocks corresponding to one of the plurality of combiners, each of the plurality of decision blocks comparing a corresponding summed signal to a predetermined value to determine the bit value of the digital message.

43. The receiver of claim 42 wherein the digital message comprises a burst of data interleaved into a plurality of transmit bits and spread across a plurality of transmit codes, combined and spreading using a scrambling sequence and transmitted in a time slot within a TDMA superframe.

44. The receiver of claim 42 wherein the selector receives a plurality of decisions only from a first demodulator bank in the plurality of demodulator banks.

45. The receiver of claim 42 further comprising a first message extractor for extracting a first message from the digital message.

46. The receiver of claim 45 further comprising a second message extractor for extracting a second message from the digital message.

47. The receiver of claim 42 wherein each of the plurality of demodulators is a noncoherent BPSK demodulator for computing the dot product of its respective one of the plurality of despread signals with itself delayed by one bit period.

48. A transmitter utilizing time division multiple access (TDMA) and code division multiplexing (CDM) techniques for efficiently transmitting bursts of data, the transmitter comprising:

a timing reference for generating a precise timing signal and a corresponding precise time reference;

an interleaving multiplexer for interleaving a burst of data into a plurality of transmit bit sets using an interleaving multiplexer;

an orthogonal spreader, the orthogonal spreader spreading the plurality of transmit bit sets across a plurality of transmit codes using a plurality of orthogonal spreading codes;

a combiner, the combiner combining the spread plurality of transmit bit sets; and

a scrambling sequence, the scrambling sequence scrambling the combined and spread plurality of transmit bit sets for transmission within a corresponding TDMA slot within a TDMA superframe.

49. The transmitter of claim 48 wherein the plurality of orthogonal spreading codes comprise Walsh codes.

50. The transmitter of claim 48 wherein the scrambling sequence comprises a Gold code.

51. The transmitter of claim 48 wherein the scrambling sequence comprises a Kasami sequence.

52. The transmitter of claim 48 wherein each burst of data includes forward error correction data bits.

53. The transmitter of claim 48 wherein each of the bursts of data comprise a first message spread across a first transmit code in the plurality of transmit codes and a second message in other of the plurality of transmit codes.

54. The transmitter of claim 48 wherein each of the bursts of data comprise a first message spread across the plurality of transmit codes.

55. The transmitter of claim 48 further comprising a modulator, the modulator modulating the plurality of transmit bit sets for transmission.

56. The transmitter of claim 48 wherein the plurality of transmit bit sets includes a first transmit bit set and other transmit bit sets, the first transmit bit set including:

a predetermined number of header bits for allowing transmitter settling and for reducing spectral splatter;

a predetermined number of preamble bits for improving a probability of reception of message bits; and

a first predetermined number of the message bits; and

a predetermined number of tail bits for allowing transmitter turn-off; and

wherein the other transmit bit sets includes a second predetermined number of message bits.

57. The transmitter of claim 56 wherein the second predetermined number of message bits is equal to the first predetermined number of message bits.

58. The transmitter of claim 56 wherein the second predetermined number of message bits is equal to at least the first predetermined number of message bits plus the predetermined number of preamble bits.

59. The transmitter of claim 56 wherein the second predetermined number of message bits is equal to the first predetermined number of message bits plus the predetermined number of preamble bits plus a predetermined number of fill bits.

60. The transmitter of claim 56 wherein the first predetermined number of message bits comprises a first message and wherein the second predetermined number of message bits comprises a second message.

61. The transmitter of claim 56 wherein the first predetermined number of message bits and the second predetermined number of message bits comprises a first message.

62. The transmitter of claim 56 wherein the preamble bits include:

signature sequence bits for providing good cross correlation properties between different CDMA channels; and

unique word bits for providing good auto correlation properties for each CDMA channel and improving bit synchronization.

63. The transmitter of claim 56 wherein the TDMA superframe includes a plurality of TDMA frames, each TDMA frame including a plurality of time slots for transmitting the bursts of data whereby each one of the plurality of transmitters is assigned (i) at least one time slot within the plurality of TDMA frames for specifying a transmit opportunity, (ii) a position for specifying a first frame within the TDMA superframe for further specifying a transmit opportunity, and (iii) an interval for specifying a number of frames between transmission of bursts of data for further specifying a transmit opportunity.