Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

• US 20050260793A1
• Filed: 04/07/2005
• Published: 11/24/2005
• Est. Priority Date: 12/07/2000
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Patel, Satyadev R., Huibers, Andrew G., Chiang, Steve S.
• Application Number:
  US11/102,214
• Publication Number:
  US 20050260793A1
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: B81B 2201/042 Micromirrors, not used as optical switches
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00214 Processes for the simultaneaous manufacturing of a network or an array of similar microstructural devices
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 1/00896 Temporary protection during separation into individual elements
• CPC Class Codes: B81C 1/00904 Multistep processes for the separation of wafers into individual elements not provided for in groups B81C1/00873 - B81C1/00896
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01054 : Xenon [Xe]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

Claims

1. A method for making a plurality of spatial light modulator, comprising:

providing a transparent wafer and a semiconductor wafer;

depositing and patterning sacrificial and structural materials on the transparent wafer or semiconductor wafer to form a plurality of micromirrors within a plurality of rectangular micromirror arrays;

removing the sacrificial material to release the plurality of micromirrors in the plurality of micromirror arrays;

wherein the micromirrors within a rectangular micromirror array of the plurality of micromirror arrays have micromirror edges that are neither parallel nor perpendicular to sides of the rectangular micromirror array;

bonding the transparent wafer and semiconductor wafer together with a spacer layer therebetween so as to form gaps in which the micromirror arrays are each disposed;

wherein the bonding is performed by an application of an adhesive, an application of pressure to press the transparent wafer and semiconductor wafer together; and

a step of curing the adhesive so as to form a wafer assembly; and

singulating the wafer assembly into individual spatial light modulators.

2. The method of claim 1, wherein the adhesive is dispensed trough a syringe.

3. The method of claim 2, wherein the syringe is moved along X-Y coordinates with adhesive forced through the syringe with positive pressure.

4. The method of claim 3, wherein the positive pressure is provided by a mechanical plunger.

5. The method of claim 3, wherein the positive pressure is provided by an air piston.

6. The method of claim 3, wherein the positive pressure is provided by an auger.

7. The method of claim 1, wherein the adhesive is deposited by printing.

8. The method of claim 1, wherein the adhesive is dispensed by automated controlled liquid dispensing through a syringe.

9. The method of claim 6, wherein the adhesive is screen printed.

10. The method of claim 6, wherein the adhesive is offset printed.

11. The method of claim 6, wherein the adhesive is roller printed.

12. The method of claim 1, wherein the adhesive is an epoxy.

13. The method of claim 12, wherein the epoxy is a UV cure epoxy.

14. The method of claim 12, wherein the epoxy is a thermal cure epoxy.

15. The method of claim 1, wherein the adhesive is a LV cure adhesive.

16. The method of claim 1, wherein the adhesive is a thermal cure adhesive.

17. The method of claim 1, wherein the spacer layer comprises microfabricated spacers.

18. The method of claim 1, wherein the spacer layer comprises pillars provided at the side of each micromirror array.

19. The method of claim 1, wherein the spacer layer comprises spacers mixed into the adhesive and deposited along with the adhesive.

20. The method of claim 19, wherein the spacers are balls or rods and the adhesive is epoxy.

21. The method of claim 1, wherein the spacer layer comprises one or more intermediate wafers with open areas corresponding to each micromirror array.

22. The method of claim 1, wherein the singulating of the wafer assembly comprises singulating the transparent and semiconductor wafers into spatial light modulators where the singulated spatial light modulator have a transparent die portion bonded to a semiconductor die portion, and wherein the transparent die portion is offset from the semiconductor die portion.

23. The method of claim 22, wherein an area on the semiconductor die portion is exposed for testing.

24. The method of claim 22, wherein an area on the semiconductor die portion is exposed and has a bond pad area with bond wires attached thereto.

25. The method of claim 24, wherein the transparent die portion is quartz.

26. The method of claim 24, wherein the transparent die portion is glass.

27. The method of claim 26, wherein the semiconductor die portion is silicon.

28. The method of claim 27, wherein the number of micromirrors in each micromirror array is from 6,000 to about 6 million.

29. The method of claim 28, wherein the wafer assembly is singulated into individual spatial light modulators by scribing and breaking.

30. The method of claim 28, wherein the singulation of the wafer assembly into individual spatial light modulators comprises sawing.

31. The method of claim 1, wherein the bonding of the transparent wafer to the semiconductor wafer comprises aligning fiducials on the wafers.

32. The method of claim 1, wherein a spatial light modulator formed after singulation is positioned within a projection display and where the micromirrors in the spatial light modulator correspond to pixels of the projection display.

33. The method of claim 1, wherein the wafer assembly is tested for abnormalities prior to singulation into individual spatial light modulators.

34. The method of claim 12, wherein the spacer layer comprises a spacing wafer between the first and second wafers.

35. The method of claim 1, wherein the plurality of rectangular micromirror arrays are formed on the semiconductor substrate.

36. The method of claim 1, further comprising applying a stiction reducing agent to one or both wafers before or after bonding the two wafers together.

37. The method of claim 36, wherein the stiction reducing agent is applied before bonding the wafers together.

38. The method of claim 36, wherein the stiction reducing agent is applied after bonding the wafers together.

39. The method of claim 38, wherein the stiction reducing agent is applied before singulating the wafer assembly into individual spatial light modulators.

40. The method of claim 38, wherein the micromirrors are formed on the semiconductor substrate.

41. The method of claim 1, wherein the singulating of the wafer assembly comprises scribing or sawing the transparent wafer and semiconductor wafer, where scribing or sawing on one wafer is offset from scribing or sawing on the other wafer.

42. The method of claim 1, wherein a light blocking mask is formed on the transparent wafer.

43. The method of claim 42, wherein when the wafer assembly is singulated into individual spatial light modulators, a light blocking mask is disposed on a transparent substrate within each spatial light modulator.

44. The method of claim 43, wherein the light blocking mask is formed as a rectangular frame around each micromirror array in each spatial light modulator.

45. The method of claim 44, further comprising packaging the spatial light modulators.

46. The method of claim 1, further comprising providing the semiconductor substrate of each spatial light modulator on a lower packaging substrate.

47. The method of claim 1, wherein the micromirrors have jagged or zig-zag edges.

48. The method of claim 1, further comprising providing a getter before bonding the two wafers together into a wafer assembly.

49. The method of claim 48, wherein the getter is a molecular, hydrogen and/or particle getter.

50. The method of claim 48, wherein the getter is a particulate and moisture getter.

51. The method of claim 48, wherein the getter is capable of absorbing moisture.

52. The method of claim 1, further comprising providing a getter prior to wafer bonding, and providing a stiction reducing agent after wafer bonding.

53. The method of claim 1, wherein the depositing and patterning of sacrificial and structural materials comprises depositing and patterning sacrificial material on the transparent or semiconductor substrate, and depositing and patterning structural material thereon so as to define micromirror plates and hinges for the plurality of micromirrors.

54. The method of claim 1, wherein some of the mirror edges of the mirrors are neither parallel nor perpendicular to the edges of the active area, and some edges are parallel to active area edges.

55. The method of claim 1, wherein the mirror edges are approximately 45 degrees relative to the active area edges.

56. The method of claim 1, wherein no mirror edges are parallel or perpendicular to edges of the active area.

57. The method of claim 56, wherein each mirror has a switching axis that is at a non-parallel and non-perpendicular angle to at least one edge of the mirror.

58. The method of claim 1, wherein each mirror has a switching axis parallel to at least one edge of the active area.

59. The method of claim 58, wherein each mirror has a switching axis at an angle of from 40 to 55 degrees to one or more edges of each mirror.

60. The method of claim 59, wherein each mirror has a front edge that is non-perpendicular to any edge of the active area.

61. The method of claim 1, wherein each mirror is a square mirror having four edges defining the square mirror, wherein the four edges of each mirror is neither parallel nor perpendicular to any edges of the active area.

62. The method of claim 61, wherein addressing rows connect to every other mirror.

63. The method of claim 61, wherein addressing columns connect to every other mirror.