Low-carbon-doped silicon oxide film and damascene structure using same

• US 20050260850A1
• Filed: 05/24/2004
• Published: 11/24/2005
• Est. Priority Date: 05/24/2004
• Status: Active Grant

• Current Assignee: ASM Japan K.K. (ASM International NV)
• Original Assignee: ASM Japan K.K. (ASM International NV)
• Inventors: Yoshioka, Kanako, Satoh, Kiyoshi, Loke, Chou San Nelson
• Granted Patent: US 7,271,093 B2
• Time in Patent Office: Days
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming an interconnect for a semiconductor device using triple hard layers, comprises: forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer; forming a second hard layer on the first hard layer; forming a dielectric layer on the second hard layer; forming a third hard layer on the dielectric layer; forming a hole through the third and second hard layers, the dielectric layer, and the first hard layer; and filling the hole with metal to establish an interconnect. The second and third hard layers are each made of carbon-doped silicon oxide formed from a source gas and a redox gas, while controlling the carbon content in the second hard layer as a function of a flow rate of the redox gas.

Claims

1. A method of forming an interconnect for a semiconductor device using triple hard layers, comprising:

(i) forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer;

(ii) forming a second hard layer on the first hard layer;

(iii) forming a dielectric layer on the second hard layer;

(iv) forming a third hard layer serving as a hard cap layer on the dielectric layer;

(v) forming a hole through the third and the second hard layers, the dielectric layer, and the first hard layer; and

(vi) filling the hole with metal to establish an interconnect.

2. The method according to claim 1, wherein the dielectric layer is comprised of a lower dielectric layer and an upper dielectric layer, wherein the hole is constituted by a via formed in the lower dielectric layer, and a trench formed in the upper dielectric layer.

3. The method according to claim 1, wherein the hole is constituted by a via formed in the second hard layer, and a trench formed in the dielectric layer.

4. The method according to claim 1, wherein the hole is constituted by a via formed in the dielectric layer, and a trench formed in the third hard layer.

5. The method according to claim 1, wherein steps (i) to (iv) are conducted in a same reaction chamber without breaking a vacuum.

6. The method according to claim 1, wherein in step (vi), the hole is filled with copper as the metal.

7. The method according to claim 1, wherein the first hard layer is made of silicon carbide.

8. The method according to claim 1, wherein the second and the third hard layers are made of carbon-doped silicon oxide.

9. The method according to claim 8, wherein the second and the third hard layers are deposited from a source gas used as a precursor of carbon-doped silicon oxide, and a redox gas which subjects the precursor to a reductive condition and an oxidizing condition in a plasma.

10. The method according to claim 9, wherein the redox gas contains carbon and oxygen.

11. The method according to claim 10, wherein the redox gas is CO₂.

12. The method according to claim 8, wherein the flow rate of the redox gas is at least 10 times that of the source gas.

13. The method according to claim 8, wherein the source gas has the formula Si_α

O<sub>α

−

1</sub>R<sub>2α

−

β

+2</sub>(OC_nH_2n+1)_β

wherein α

is an integer of 1-3, β

is an integer of 1-3, n is an integer of 1-3, and R is C_1-6 hydrocarbon attached to Si.

14. The method according to claim 8, wherein the second and the third hard layers are formed using a plasma generated by a coupled frequency of about 27 MHz and about 400 kHz.

15. The method according to claim 8, wherein the second and the third hard layers are formed at a substrate temperature of about 100°

C. to about 400°

C.

16. The method according to claim 8, wherein the redox gas and the source gas are introduced into a reaction chamber through the a same gas line controlled at a temperature at which the redox gas and the source gas do not react.

17. The method according to claim 16, wherein the temperature is about 50°

C. to about 240°

C.

18. The method according to claim 8, wherein the second and the third hard layers are formed without using an inert gas.

19. The method according to claim 8, wherein the second and the third hard layers are formed at a pressure of about 100 Pa to about 1,000 Pa.

20. A method of forming an interconnect for a semiconductor device using triple hard layers, comprising:

(i) forming a first hard layer serving as an etch stop layer on a copper interconnect-formed dielectric layer, said first hard layer being made of silicon carbide;

(ii) forming a second hard layer on the first hard layer, which is made of carbon-doped silicon oxide;

(iii) forming a dielectric layer on the second hard layer;

(iv) forming a third hard layer serving as a hard cap layer on the dielectric layer, which is made of carbon-doped silicon oxide, wherein steps (i) to (iv) are conducted in a same reaction chamber without breaking a vacuum;

(v) forming a hole through the third and second hard layers, the dielectric layer, and the first hard layer; and

(vi) filling the hole with copper to establish an interconnect.

21. The method according to claim 20, wherein the dielectric layer is comprised of a lower dielectric layer and an upper dielectric layer, wherein the hole is constituted by a via formed in the lower dielectric layer, and a trench formed in the upper dielectric layer.

22. The method according to claim 20, wherein the hole is constituted by a via formed in the second hard layer, and a trench formed in the dielectric layer.

23. The method according to claim 20, wherein the hole is constituted by a via formed in the dielectric layer, and a trench formed in the third hard layer.

24. The method according to claim 20, wherein the second and the third hard layers are deposited from a source gas used as a precursor of carbon-doped silicon oxide, and a redox gas which subjects the precursor to a reductive condition and an oxidizing condition in a plasma.

25. The method according to claim 24, wherein the source gas contains silicon, carbon, hydrogen, and optionally oxygen, and the redox gas contains carbon and oxygen.

26. The method according to claim 25, wherein the redox gas is CO₂.

27. The method according to claim 20, wherein the flow rate of the redox gas is at least 10 times that of the source gas.

28. The method according to claim 20, wherein the source gas has the formula Si_α

O<sub>α

−

1</sub>R<sub>2α

−

β

+2</sub>(OC_nH_2n+1)_β

wherein α

is an integer of 1-3, β

is an integer of 1-3, n is an integer of 1-3, and R is C_1-6 hydrocarbon attached to Si.

29. The method according to claim 20, wherein the second and the third hard layers are formed using a plasma generated by a coupled frequency of about 27 MHz and about 400 kHz, at a substrate temperature of about 100°

C. to about 400°

C., and at a pressure of about 100 Pa to about 1,000 Pa.

30. The method according to claim 20, wherein the redox gas and the source gas are introduced together into a reaction chamber at a temperature of about 50°

C. to about 240°

C.

31. The method according to claim 20, wherein the second and the third hard layers are formed without using an inert gas.

32. A method of forming an interconnect for a semiconductor device using triple hard layers, comprising:

(i) forming a first hard layer serving as an etch stop layer on a metal interconnect-formed dielectric layer;

(ii) forming a second hard layer on the first hard layer, which is made of carbon-doped silicon oxide formed from a source gas and a redox gas, while controlling the carbon content in the second hard layer as a function of a flow rate of the redox gas;

(iii) forming a dielectric layer on the second hard layer;

(iv) forming a third hard layer on the dielectric layer, which is made of carbon-doped silicon oxide formed from a source gas and a redox gas, while controlling the carbon content in the third hard layer as a function of a flow rate of the redox gas;

(v) forming a hole through the third and second hard layers, the dielectric layer, and the first hard layer; and

(vi) filling the hole with metal to establish an interconnect.

33. The method according to claim 32, wherein in steps (ii) and (iv), the flow rate of the redox gas is at least 10 times that of the source gas.

34. The method according to claim 32, wherein in steps (ii) and (iv), no inert gas is used.

35. An interconnect structure for a semiconductor device, comprising:

a copper-filled dielectric layer;

a first hard layer serving as an etch stop layer formed on the copper-filled dielectric layer;

a second hard layer formed on the first hard layer;

a dielectric layer formed on the second hard layer;

a third hard layer serving as a hard cap layer formed on the dielectric layer; and

a copper interconnect which is filled in a hole formed through the third and second hard layers, the dielectric layer, and the first hard layer.

36. The structure according to claim 35, wherein the dielectric layer is comprised of a lower dielectric layer and an upper dielectric layer, wherein the hole is constituted by a via formed in the lower dielectric layer, and a trench formed in the upper dielectric layer.

37. The structure according to claim 35, wherein the hole is constituted by a via formed in the second hard layer, and a trench formed in the dielectric layer.

38. The structure according to claim 35, wherein the hole is constituted by a via formed in the dielectric layer, and a trench formed in the third hard layer.

39. The structure according to claim 35, wherein adhesion between the first hard layer and the second hard layer is above 10 J/m².

40. The structure according to claim 35, wherein the first, second, and third hard layers and the dielectric layer have a total thickness of about 100 nm to about 20,000 nm.

41. The structure according to claim 35, wherein the third hard layer has a thickness which is about 2% to about 20% of the dielectric layer.

42. The structure according to claim 35, wherein the first hard layer has compressive stress, and the second hard layer has tensile stress.

43. The structure according to claim 35, wherein the second and the third hard layers each have carbon in an amount of less than 20%.

44. The structure according to claim 35, wherein the second and the third hard layers each have a dielectric constant of about 3.5 or less.

45. The structure according to claim 35, wherein the second and the third hard layers each have a refractive index (R.I.) of about 1.2 to about 1.7.

46. The structure according to claim 35, wherein the second and the third hard layers are each anti-refractive at a wavelength of 193 nm or less.

47. The structure according to claim 35, wherein the second and the third hard layers each have a hardness of about 2.0 GPa to about 4.0 GPa and an elastic modulus of about 10 GPa to about 30 GPa.

48. The structure according to claim 35, wherein the third hard layer has a polishing rate which is about ⅕

to about 1/10 of that of the dielectric layer.

49. The structure according to claim 35, wherein the hole has a periphery wall formed substantially at 90°

with respect to a plane of the layers.

50. The structure according to claim 35, wherein the dielectric layer has a stress of about 45 MPa to about 80 MPa tensile.

51. The structure according to claim 35, wherein the second and the third hard layers each have an area ratio of Si—

CH₃ to Si—

O of about 1.5 to 2.5 in FTIR spectra.

52. The structure according to claim 35, wherein the second and the third hard layers each have an area ratio of Si—

C/Si—

O of about 7 to about 15 in FTIR spectra.

53. The structure according to claim 35, wherein the second and the third hard layers each have an area ratio —

C—

H/Si—

O of about 0.5 to about 1.5 in FTIR spectra.