I/O configuration messaging within a link-based computing system

• US 20050262391A1
• Filed: 05/10/2004
• Published: 11/24/2005
• Est. Priority Date: 05/10/2004
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sethi, Prashant, Creta, Kenneth C.
• Application Number:
  US10/843,286
• Publication Number:
  US 20050262391A1
• Time in Patent Office: Days
• US Class Current: 714/9
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A method is described that comprises uses at least a portion of a configuration transaction address to perform a look-up into a memory. The configuration transaction is to perform a configuration function at an I/O Unit connected to an I/O segment within a link-based computing system. The look-up is to identify a component within the link-based computing system. The I/O segment is accessed through the component within the link-based computing system.

Claims

1. A method, comprising:

using at least a portion of a configuration transaction address to perform a look-up into a memory, said configuration transaction to perform a configuration function at an I/O Unit connected to an I/O segment within a link-based computing system, said look-up to identify a component within said link-based computing system, said I/O segment accessed through said component within said link-based computing system.

2. The method of claim 1 wherein said I/O segment is one of a plurality of I/O segments within said link-based computing system.

3. The method of claim 2 wherein said portion specifically identifies said I/O segment from amongst said plurality of I/O segments.

4. The method of claim 1 wherein said configuration transaction is a read configuration transaction that reads information from said I/O unit.

5. The method of claim 1 wherein said configuration transaction is a write configuration transaction that writes information into said I/O unit.

6. The method of claim 1 wherein said configuration transaction address comprises a parameter that identifies a bus or a link within said I/O segment.

7. The method of claim 1 wherein said configuration transaction address comprises a parameter that identifies said I/O unit.

8. The method of claim 1 wherein said configuration transaction address comprises a parameter that identifies said configuration function to be performed at said I/O unit.

9. The method of claim 1 wherein said configuration transaction address comprises a parameter that identifies specific register space within said I/O unit.

10. The method of claim 1 wherein said method further comprises forming a packet that includes a destination parameter that identifies said packet'"'"'s destination, said destination parameter identifying said component, said packet also containing parameters that said I/O segment can understand and are directed to performing said configuration function at said I/O unit.

11. The method of claim 10 further comprising receiving said packet at said component and performing said configuration function at said I/O unit.

12. The method of claim 11 further comprising sending a second packet from said component to a second component within said link-based computing system where said using was performed, said packet further containing an identification of said second component as the sender of said packet, said second packet containing said identification as the destination of said second packet.

13. The method of claim 12 wherein said configuration function is a read function and said second packet contains information read from said I/O unit.

14. An apparatus, comprising:

a source address decoder comprising look-up logic circuitry and memory circuitry, said source address decoder having input wiring to at least receive a portion of a configuration transaction address, said configuration transaction to perform a configuration function at an I/O Unit connected to an I/O segment within a link-based computing system, said source decoder having output wiring to present an identification of a component within said link-based computing system, said I/O segment accessed through said component within said link-based computing system.

15. The apparatus of claim 14 wherein said I/O segment is one of a plurality of I/O segments within said link-based computing system.

16. The apparatus of claim 15 wherein said portion specifically identifies said I/O segment from amongst said plurality of I/O segments.

17. The apparatus of claim 14 wherein said configuration transaction can be a read configuration transaction that reads information from said I/O unit.

18. The method of claim 14 wherein said configuration transaction can be a write configuration transaction that writes information into said I/O unit.

19. The apparatus of claim 14 wherein said configuration transaction address comprises a parameter that identifies a bus or a link within said I/O segment.

20. The apparatus of claim 14 wherein said configuration transaction address comprises a parameter that identifies said I/O unit.

21. The apparatus of claim 14 wherein said configuration transaction address comprises a parameter that identifies a function to be performed at said I/O unit.

22. The apparatus of claim 14 wherein said configuration transaction address comprises a parameter that identifies specific register space within said I/O unit.

23. An apparatus, comprising:

link-based computing system comprising a first component communicatively coupled through a network to a second component, said network comprised of copper cabling to transport information between said first and second components, said first component comprised of a source address decoder comprising look-up logic circuitry and memory circuitry, said source address decoder having input wiring to at least receive a portion of a configuration transaction address, said configuration transaction to perform a configuration function at an I/O Unit connected to an I/O segment accessed through said second component, said source decoder having output wiring to present an identification of said second component.

24. The apparatus of claim 23 wherein said I/O segment is one of a plurality of I/O segments within said link-based computing system.

25. The apparatus of claim 24 wherein said portion specifically identifies said I/O segment from amongst said plurality of I/O segments.

26. The apparatus of claim 23 wherein said configuration transaction can be a read configuration transaction that reads information from said I/O unit.

27. The method of claim 23 wherein said configuration transaction can be a write configuration transaction that writes information into said I/O unit.

28. The apparatus of claim 23 wherein said configuration transaction address comprises a parameter that identifies a bus or a link within said I/O segment.

29. The apparatus of claim 23 wherein said configuration transaction address comprises a parameter that identifies said I/O unit.

30. The apparatus of claim 23 wherein said configuration transaction address comprises a parameter that identifies a function to be performed at said I/O unit.

31. The apparatus of claim 23 wherein said configuration transaction address comprises a parameter that identifies specific register space within said I/O unit.