Apparatus and method for reducing test resources in testing DRAMs

• US 20050262405A1
• Filed: 07/25/2005
• Published: 11/24/2005
• Est. Priority Date: 12/03/1999
• Status: Abandoned Application

• Current Assignee: Chris Cooper, David R. Brown, Jerry D. Mcbride, Scott L. Ayres, Scott N. Gatzemeier, Siang Tian Giam
• Original Assignee: Chris Cooper, David R. Brown, Jerry D. Mcbride, Scott L. Ayres, Scott N. Gatzemeier, Siang Tian Giam
• Inventors: Gatzemeier, Scott N., Brown, David R., Ayres, Scott L., Cooper, Chris, McBride, Jerry D., Giam, Siang Tian
• Application Number:
  US11/188,932
• Publication Number:
  US 20050262405A1
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31932 Comparators
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

Claims

1. A probe for testing a computer memory device, the probe comprising:

a plurality of pins configured to positionally align with at least one memory device to be tested, the plurality of pins having a control pin configured to output to the at least one memory device a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal.

2. The probe of claim 1, wherein the plurality of pins comprises 100 pins.

3. The probe of claim 1, wherein the memory device to be tested comprises a Rambus dynamic random access memory (RDRAM).

4. The probe of claim 1, wherein the plurality of pins is configured to positionally align with a plurality of memory devices to be tested.

5. The probe of claim 4, wherein the plurality of memory devices to be tested comprises at least three memory devices.

6. The probe of claim 1, wherein the first portion of the control signal is a leading edge of the control signal.

7. The probe of claim 6, wherein the second portion of the control signal is a trailing edge of the control signal.

8. The probe of claim 1, wherein the plurality of pins comprises at most nine address pins configured to output address bits to the memory device to be tested.

9. The probe of claim 1, wherein the plurality of pins comprises at most four data pins configured to output data bits to the memory device to be tested.

10. The probe of claim 1, further comprising read circuitry configured to read data from the memory device.

11. The probe of claim 1, further comprising compare circuitry configured to compare data read from the memory device with test data in order to test the integrity of the memory device.

12. A wafer probe for testing a plurality of computer memory devices configured on a semiconductor wafer, the wafer probe comprising:

a plurality of pins having tip ends configured to positionally align with a plurality of memory devices to be tested, the plurality of pins having a control pin for each of the plurality of memory devices to be tested, wherein each control pin is configured to output to each of the memory devices to be tested a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal.

13. The wafer probe of claim 12, wherein the plurality of pins comprises 100 pins.

14. The wafer probe of claim 12, wherein the plurality of memory devices to be tested comprises Rambus dynamic random access memory (RDRAM).

15. The wafer probe of claim 12, wherein the plurality of memory devices to be tested comprises at least three memory devices.

16. The wafer probe of claim 12, wherein the first portion of the control signal is a leading edge of the control signal.

17. The wafer probe of claim 16, wherein the second portion of the control signal is a trailing edge of the control signal.

18. The wafer probe of claim 12, wherein the plurality of pins comprises at most nine address pins for each of the memory devices to be tested, wherein the address pins are configured to output address bits to each of the memory devices to be tested.

19. The wafer probe of claim 12, wherein the plurality of pins comprises at most four data pins for each of the plurality of memory devices to be tested, wherein the data pins are configured to output data bits to each of the memory devices to be tested.

20. The wafer probe of claim 12, further comprising read circuitry configured to read data from each of the plurality of memory devices.

21. The wafer probe of claim 12, further comprising compare circuitry configured to compare data read from each of the plurality of memory devices with test data in order to test the integrity of each of the plurality of memory devices.

22. An apparatus for testing a computer memory device, the apparatus comprising:

a probe having a plurality of pins configured to positionally align with a memory device to be tested, the plurality of pins having a control pin configured to output to the memory device a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal, wherein the plurality of pins further comprises address pins configured to output to the memory device address bits identifying at least one location within the memory device;

read circuitry configured to read data from the memory device, wherein the data is stored at the at least one location identified by the address bits; and

compare circuitry configured to compare the data read from the memory device with test data in order to test the integrity of the memory device.

23. The apparatus of claim 22, wherein the plurality of pins comprises 100 pins.

24. The apparatus of claim 22, wherein the memory device comprises a Rambus dynamic random access memory (RDRAM).

25. The apparatus of claim 22, wherein the plurality of pins is configured to positionally align with a plurality of memory devices to be tested.

26. The apparatus of claim 22, wherein the first portion of the control signal is a leading edge of the control signal.

27. The apparatus of claim 22, wherein the second portion of the control signal is a trailing edge of the control signal.