Apparatus and method for decoding low density parity check codes

• US 20050262420A1
• Filed: 05/20/2005
• Published: 11/24/2005
• Est. Priority Date: 05/21/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Sung-Jin, Kim, Min-Goo, Yu, Nam Yul, Kim, Han-Ju
• Granted Patent: US 7,631,241 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: H03M 13/1137 Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions

Abstract

An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.

Claims

1. An apparatus for decoding low density parity check (LDPC) codes, comprising:

a plurality of variable node processors each reading data stored in a memory module in a column direction, computing a probability value of a variable node, and storing the computed probability value in the memory module in the column direction;

a plurality of check node processors each reading data stored in the memory module in a row direction, computing a probability value of a check node, and storing the computed probability value in the memory module in the row direction;

a parity checker connected to the plurality of check node processors for receiving data from the plurality of check node processors, and determining if a decoding process is successful;

the memory module for storing a hard decision bit and a soft metric value in an identical memory address after a computation of each check node processor is performed, the memory module being configured by a plurality of unit memories to be accessed by the plurality of variable node processors and the plurality of check node processors; and

a memory access control module for generating an enable signal and a memory address signal for storing the hard decision bit and the soft metric value after a computation of each variable node processor is performed.

2. The apparatus of claim 1, wherein the memory access control module comprises:

a write enable controller for generating the enable signal; and

an address index generator for generating the memory address signal.

3. The apparatus of claim 1, wherein the memory access control module comprises:

an address index generator for outputting, to a unit memory, an address mapped to each node processor; and

a write enable controller for controlling an operation for enabling a computation for a specific unit memory of the plurality of unit memories.

4. The apparatus of claim 1, wherein the plurality of unit memories are connected to

multiplexers and demultiplexers such that an input and output are enabled selectively.

5. The apparatus of claim 1, wherein the apparatus comprises a low density parity check decoder.

6. The apparatus of claim 5, wherein the LDPC decoder is implemented in a parallel structure.

7. The apparatus of claim 1, wherein the plurality of check node processors determine if all errors are corrected.

8. The apparatus of claim 1, wherein the parity checker performs iterative decoding.

9. A method for decoding low density parity check (LDPC) codes, comprising the steps of:

initializing memories and registers to zero;

storing received symbols in the memories;

performing a computation of at least one check node processor in a row direction, and storing a hard decision bit and a soft metric value in an identical memory address;

determining if a decoding process is successful, and performing a parity check operation using the hard decision bit; and

performing a computation of at least one variable node processor if the decoding process is successful.

10. The method of claim 9, further comprising the step of:

performing the computation of the at least one variable node processor and an iterative computation if the decoding process fails.

11. The method of claim 10, further comprising the step of:

performing an iterative decoding process before the computation of the at least one check node processor.