System and method for verifying a layout of circuit traces on a motherboard

• US 20050262455A1
• Filed: 10/29/2004
• Published: 11/24/2005
• Est. Priority Date: 05/21/2004
• Status: Active Grant

• Current Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Hon Hai Precision Industry Co., Ltd.
• Inventors: Wu, Hao, Peng, Jie, Lin, Yu-Long
• Granted Patent: US 7,219,318 B2
• Time in Patent Office: Days
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A system for verifying a layout of circuit traces on a motherboard includes a computer (1) and a database (2). The database is used for storing data generated and used by the system. The computer includes: a substandard layout area creating module (101) for creating substandard layout areas; a substandard segment data obtaining module (102) for obtaining from the database actual layout data on substandard segments placed in the substandard areas; a substandard length calculating module (103) for calculating a total length of all the substandard segments of a trace; and a satisfactory trace determining module (104) for comparing the total length of the substandard segments of the trace with a preset standard length for the trace, and determining whether the trace is satisfactory. A related method is also disclosed.

Claims

1. A system for verifying a layout of traces on a motherboard, the system comprising a computer and a database connected to the computer, wherein:

the database comprises;

a standard layout data storage for storing preset standard layout data on segments of the traces and a preset standard length for each of the traces; and

an actual layout data storage for storing actual layout data on the segments of the traces; and

the computer comprises;

a substandard layout area creating module for creating substandard areas according the standard layout data on the segments of the traces and split planes next to the traces;

a substandard segment data obtaining module for obtaining actual layout data on substandard segments from the actual layout data storage, wherein the substandard segments are placed in the substandard areas;

a substandard length calculating module for calculating a length for each substandard segment of each of the traces and a total length of the substandard segments of the trace; and

a satisfactory trace determining module for determining whether each of the traces is satisfactory by comparing the total length of substandard segments of the trace with the preset standard length for the trace.

2. The system according to claim 1, further comprising a connection connecting the computer with the database.

3. The system according to claim 1, wherein the preset standard layout data on each segment comprises a standard layout space, a standard layout width, and standard start coordinate values and end coordinate values of the segment.

4. The system according to claim 1, wherein the actual layout data on each segment comprises an identifier, an actual width, and actual start coordinate values and end coordinate values of the segment.

5. The system according to claim 1, wherein the motherboard comprises a printed circuit board (PCB) on which there are distributed a plurality of traces, a plurality of split planes, and a plurality of areas having a same voltage.

6. The system according to claim 5, wherein the split planes comprise dielectric-filled moats between the areas having a same voltage, etched areas, and board edges of the PCB.

7. A computer-based method for verifying a layout of a trace on a motherboard, the method comprising the steps of:

obtaining standard layout data on segments of the trace and a preset standard length for the trace;

creating substandard areas according to the standard layout data on the segments of the trace and split planes next to the trace;

obtaining actual layout data on all substandard segments of the trace, wherein the substandard segments are placed in the substandard areas;

calculating a length for each of the substandard segments;

adding up all the lengths of the substandard segments to obtain a total length;

determining whether the total length exceeds the preset standard length; and

generating a report about how to modify the trace if the total length exceeds the preset standard length.

8. The method according to claim 7, wherein the standard layout data on each segment of the trace comprises a standard layout space, a standard layout width, and standard start coordinate values and end coordinate values of the segment.

9. The method according to claim 7, wherein the actual layout data on each segment of the trace comprises an identifier, an actual width, and actual start coordinate values and end coordinate values of the segment.

10. The method according to claim 7, further comprising the step of accepting the trace as a satisfactory trace if the total length of the substandard segments of the trace does not exceed the preset standard length.

11. A method for verifying a trace layout of a circuit board, the method comprising the steps of:

providing a standard layout data of said trace layout and a preset permissible total length value for said trace layout;

identifying substandard areas of said trace layout in comparison with said standard layout data;

calculating a length for each of said substandard areas;

adding up said length of said each substandard area to obtain a total length; and

reporting said trace layout as failure in case that said total length is larger than said permissible total length value.

12. The method according to claim 11, wherein said standard layout data comprises a standard layout space for said trace layout away from a split plane of said circuit board, a standard layout width of said trace layout, and standard start coordinate values and end coordinate values of a segment of said trace layout for identification in said identifying step.