Packet timing method and apparatus of a receiver system for controlling digital TV program start time

• US 20050262537A1
• Filed: 05/31/2005
• Published: 11/24/2005
• Est. Priority Date: 12/27/2001
• Status: Abandoned Application

• Current Assignee: John Pickens, Michael Field, Paul Baran, Xu Duan Lin
• Original Assignee: John Pickens, Michael Field, Paul Baran, Xu Duan Lin
• Inventors: Pickens, John, Field, Michael, Lin, Xu Duan, Baran, Paul
• Application Number:
  US11/141,693
• Publication Number:
  US 20050262537A1
• Time in Patent Office: Days
• US Class Current: 725/88
• CPC Class Codes: H04L 63/068 using time-dependent keys, e.g. periodically changing keys cryptographic mechanisms or cryptographic arrangements for controlling usage of secret information H04L9/088
• CPC Class Codes: H04L 63/10 for controlling access to devices or network resources
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 65/612 for unicast
• CPC Class Codes: H04N 21/2318 using striping
• CPC Class Codes: H04N 21/2326 Scheduling disk or memory reading operations
• CPC Class Codes: H04N 21/23406 involving management of server-side video buffer
• CPC Class Codes: H04N 21/2347 involving video stream encryption
• CPC Class Codes: H04N 21/2362 Generation or processing of Service Information [SI]
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/26606 for generating or managing entitlement messages, e.g. Entitlement Control Message [ECM] or Entitlement Management Message [EMM] arrangements for conditional access to broadcast information or to broadcast-related services H04H60/14
• CPC Class Codes: H04N 21/4347 Demultiplexing of several video streams
• CPC Class Codes: H04N 21/47202 for requesting content on demand, e.g. video on demand
• CPC Class Codes: H04N 21/6405 Multicasting data broadcast and multicast in packet switching networks H04L12/18
• CPC Class Codes: H04N 21/6587 Control parameters, e.g. trick play commands, viewpoint selection
• CPC Class Codes: H04N 7/17318 Direct or substantially direct transmission and handling of requests
• CPC Class Codes: H05K 1/0275 Security details, e.g. tampering prevention or detection
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/10151 Sensor

Abstract

A packet timing method and apparatus for use with a system for controlling digital TV program start time. An encoder inserts a program clock reference (PCR) timing field, in at least two intervals in transport packets. A decoder generates a decoder-clock signal from the PCR timing signal, which has the same frequency as an encoder-clock signal used for encoding. In response to the PCR timing field, a rate of consumption of data is synchronized with a rate of production of data, and chroma sub-carrier is synchronized.

Claims

1-34. -34. (canceled)

35. A method for scheduling a packet to produce a valid multi-program transport stream (MPTS) transport packet, comprising the steps of:

inserting, at an encoder, a program clock reference (PCR) timing field having a plurality of bits, in at least two intervals in transport packets;

generating, at a decoder, responsive to the PCR timing field, a decoder-clock signal having a same frequency as an encoder-clock signal used for encoding;

synchronizing, at the decoder, responsive to the PCR timing field, a rate of consumption of data with a rate of production of data;

synchronizing, at the decoder, responsive to the PCR timing field, elementary streams; and

generating, at the decoder, responsive to the PCR timing field, a chroma-clock signal for controlling a chroma sub-carrier.

36. The method as set forth in claim 35, further including the step of synchronizing the rate of consumption to the decoder-clock signal.

37. The method as set forth in claim 35, further comprising the step of shifting a time value in an output transport packet to a same time as an input transport packet, thereby adjusting a phase difference between the output transport packet and the input transport packet.

38. A method for scheduling a packet to produce a valid multi-program transport stream (MPTS) transport packet, comprising the steps of:

inserting, at an encoder, a program clock reference (PCR) timing field having a plurality of bits, in at least two intervals in transport packets;

generating, at a decoder, responsive to the PCR timing field, a decoder-clock signal having a same frequency as an encoder-clock signal used for encoding;

synchronizing, at the decoder, responsive to the PCR timing field, a rate of consumption of data with a rate of production of data;

synchronizing, at the decoder, responsive to the PCR timing field, elementary streams; and

synchronizing, responsive to the PCR timing field, a chroma-clock signal for controlling a chroma sub-carrier.

39. The method as set forth in claim 38, further including the step of synchronizing the rate of consumption to the decoder-clock signal.

40. The method as set forth in claim 38, further comprising the step of shifting a time value in an output transport packet to a same time as an input transport packet, thereby adjusting a phase difference between the output transport packet and the input transport packet.

41. A method for scheduling a packet to produce a valid multi-program transport stream (MPTS) transport packet, comprising the steps of:

inserting, at an encoder, a program clock reference (PCR) timing field having a plurality of bits, in at least two intervals in each single-program transport stream (SPTS) transport packet of a plurality of SPTS transport packets;

storing the plurality of SPTS transport packets in a memory;

multiplexing, from the memory, the plurality of SPTS transport packets to a multi-program transport stream MPTS transport packet;

generating, at a decoder, responsive to the PCR timing field, a decoder-clock signal having a same frequency as an encoder-clock signal used for encoding;

synchronizing, at the decoder, responsive to the PCR timing field, a rate of consumption of data with a rate of production of data;

synchronizing, at the decoder, responsive to the PCR timing field, elementary streams; and

synchronizing, at the decoder, responsive to the PCR timing field, a chroma-clock signal for controlling chroma sub-carrier.

42. The method as set forth in claim 41, further including the step of synchronizing the rate of consumption to the decoder-clock signal.

43. The method as set forth in claim 41, further comprising the step of shifting a time value in an output transport packet to a same time as an input transport packet, thereby adjusting a phase difference between the output transport packet and the input transport packet.

44. An apparatus for scheduling a packet to produce a valid multi-program transport stream (MPTS) transport packet, comprising:

an encoder for inserting a program clock reference (PCR) timing field having a plurality of bits, in at least two intervals in transport packets; and

a decoder, responsive to the PCR timing field, for generating a decoder-clock signal having a same frequency as an encoder-clock signal used for encoding, for synchronizing responsive to the PCR timing field, a rate of consumption of data with a rate of production of data and for generating, responsive to the PCR timing field, a chroma-clock signal for controlling a chroma sub-carrier.

45. The apparatus as set forth in claim 44, with the decoder further for synchronizing the rate of consumption to the decoder-clock signal.

46. The apparatus as set forth in claim 44, with the decoder further for shifting a time value in an output transport packet to a same time as an input transport packet, thereby adjusting a phase difference between the output transport packet and the input transport packet.

47. An apparatus for scheduling a packet to produce a valid multi-program transport stream (MPTS) transport packet, comprising:

an encoder for inserting a program clock reference (PCR) timing field having a plurality of bits, in at least two intervals in transport packets; and

a decoder, responsive to the PCR timing field, for generating a decoder-clock signal having a same frequency as an encoder-clock signal used for encoding, and responsive to the PCR timing field, for synchronizing a rate of consumption of data with a rate of production of data, and responsive to the PCR timing field, for synchronizing a chroma-clock signal for controlling a chroma sub-carrier.

48. The apparatus as set forth in claim 47, with the decoder further for synchronizing the rate of consumption to the decoder-clock signal.

49. The apparatus as set forth in claim 47, with the decoder further for shifting a time value in an output transport packet to a same time as an input transport packet, thereby adjusting a phase difference between the output transport packet and the input transport packet.

50. An apparatus for scheduling a packet to produce a valid multi-program transport stream (MPTS) transport packet, comprising:

encoder means for inserting a program clock reference (PCR) timing field having a plurality of bits, in at least two intervals in each single-program transport stream (SPTS) transport packet of a plurality of SPTS transport packets;

memory means for storing the plurality of SPTS transport packets in a memory;

multiplexer means for multiplexing, from the memory means, the plurality of SPTS transport packets to a multi-program transport stream MPTS transport packet;

decoder means, responsive to the PCR timing field, for generating a decoder-clock signal having a same frequency as an encoder-clock signal used for encoding, and responsive to the PCR timing field, for synchronizing a rate of consumption of data with a rate of production of data, and responsive to the PCR timing field, for generating a chroma-clock signal for controlling a chroma sub-carrier.

51. The apparatus as set forth in claim 50, with the decoder means for synchronizing the rate of consumption to the decoder-clock signal.

52. The apparatus as set forth in claim 50, with the decoder means for shifting a time value in an output transport