Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same

• US 20050263762A1
• Filed: 07/08/2005
• Published: 12/01/2005
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Granted Patent: US 7,379,148 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2201/50 Protective arrangements
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate

Abstract

In an amorphous silicon thin film transistor-liquid crystal display device and a method of manufacturing the same, gate patterns including a gate line and a gate electrode are formed on an insulation substrate having a display region and a driving circuit region on which a plurality of shift registers are formed, a gate insulating film, active layer patterns and data patterns including source and drain electrodes are formed successively on the substrate, a passivation layer on the substrate has a first contact hole exposing a drain electrode of the display region and second and third contact holes respectively exposing a gate electrode and source and drain electrodes of a first transistor of each of the shift registers, an electrode patterns on the passivation layer include a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode to the source and drain electrodes of the first transistor through the second and third contact holes, and the gate driving circuit including the shift registers and the wirings are integrated on the insulating substrate without an additional process, thereby simplifying the manufacturing process.

Claims

1. A substrate for a display device, comprising:

a base substrate including a display region and a driving circuit region;

a plurality of switching transistors formed in the display region, each of the switching transistors including amorphous silicon;

a plurality of driving transistors formed in the driving circuit region, each of the driving transistors including amorphous silicon; and

a protection layer formed on the base substrate to cover the switching transistors and the driving transistors; and

an electrode pattern formed on the protection layer, the electrode pattern including a pixel electrode electrically connected to one of the switching transistors, and a connecting electrode electrically connecting two of the driving transistors.

2. The substrate of claim 1, wherein the electrode pattern comprises an optically transparent and electrically conductive material.

3. The substrate of claim 2, wherein the electrode pattern comprises at least one of ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

4. The substrate of claim 1, further comprising main signal lines for applying signals to the driving transistors, wherein the main signal lines comprise a first signal line being adjacent to the driving transistors and having a first width, and a second signal line being adjacent to the first wiring having a second width that is wider than the first width.

5. The substrate of claim 4, wherein each of the driving transistors and the switching transistors comprises a gate electrode, a drain electrode and a source electrode, and the gate electrode and the main signal lines are made of a same material.

6. The substrate of claim 5, further comprising a branch signal line extended from one of the drain electrode and the source electrode, the branch signal line including a wiring portion having a third width, and a connecting pad portion having a fourth width that is wider than the third width.

7. The substrate of claim 6, wherein the connecting pad portion is electrically connected to the connecting electrode.

13. The LCD device of claim 1.2, further comprising a branch signal line extended from one of the drain electrode and the source electrode, the branch signal line including a wiring portion having a third width, and a connecting pad portion having a fourth width that is wider than the third width.

14. The LCD device of claim 13, wherein the connecting pad portion is electrically connected to the connecting electrode.

8. A liquid crystal display (LCD) device comprising:

a first substrate including;

a base substrate including a display region and a driving circuit region;

a plurality of switching transistors formed in the display region, each of the switching transistors including amorphous silicon;

a plurality of driving transistors formed in the driving circuit region, each of the driving transistors including amorphous silicon; and

a protection layer formed on the base substrate to cover the switching transistors and the driving transistors; and

an electrode pattern formed on the protection layer, the electrode pattern including a pixel electrode electrically connected to one of the switching transistors, and a connecting electrode electrically connecting two of the driving transistors;

a second substrate facing the first substrate; and

a liquid crystal layer disposed between the first and the second substrates.

9. The LCD device of claim 8, wherein the electrode pattern comprises an optically transparent and electrically conductive material.

10. The substrate of claim. 9, wherein the electrode pattern comprises at least one of ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

11. The LCD device of claim 8, further comprising main signal lines for applying signals to the driving, wherein the main signal lines comprise a first signal line being adjacent to the driving transistors and having a first width, and a second signal line being adjacent to the first wiring having a second width that is wider than the first width.

12. The LCD device of claim 11, wherein each of the driving transistors and the switching transistors comprises a gate electrode, a drain electrode and a source electrode, and the gate electrode and the main signal lines are made of a same material.

15. A method of manufacturing a substrate for a display device, comprising:

forming a gate electrode layer on a base substrate having a display region and a driving circuit region;

patterning the gate electrode layer to form gate electrodes of switching transistors in the display region, gate electrodes of driving transistors in the driving circuit region and a main signal line in the driving circuit region;

forming a gate insulation layer on the base substrate to cover the gate electrodes of the driving transistors and the switching transistors, and the main signal line;

forming an active layer pattern on the gate insulation layer;

forming a data electrode layer on the active layer pattern and the gate insulation layer;

patterning the data electrode layer to form drain and source electrodes of the switching transistors in the display region, drain and source electrodes of the driving transistors in the driving circuit region, and a branch signal line extended from one of the drain and source electrodes of the driving transistors;

forming a passivation layer on the base substrate;

forming a first contact hole that exposes a portion of the main signal line, and a second contact hole that exposes a portion of the branch signal line;

forming a electrode layer on the passivation layer; and

patterning the electrode layer to form pixel a electrode electrically connected to one of the drain electrodes of the switching transistors, a first connecting electrode connecting two of the driving transistors, and a second connecting electrode connecting the main signal line and one of the driving transistors.

16. The method of claim 15, wherein the pixel electrode pattern comprises metal.

17. The method of claim 15, wherein the electrode pattern comprises an optically transparent and electrically conductive material.

18. The method of claim 15, wherein the gate electrode layer comprises a chromium (Cr) metal layer and aluminum (Al)-including metal layer.

19. The method of claim 18, wherein a thickness of the aluminum—

including metal layer is thicker than a thickness of the chromium metal layer

20. The method of claim 15, wherein the data electrode layer comprises a chromium metal layer and has a thickness of about 1500 angstroms to about 4000 angstroms.