Semiconductor device and method for manufacturing the same
First Claim
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1. A semiconductor device comprising:
- a first transistor comprising;
a first semiconductor region;
a first insulating film formed over the first semiconductor region;
a floating gate electrode formed over the first insulating film;
a second insulating film formed over the floating gate electrode, and a first gate electrode formed over the second insulating film; and
a second transistor comprising;
a second semiconductor region;
a third insulating film formed over the second semiconductor region; and
a second gate electrode formed over the third insulating film;
wherein the first transistor and the second transistor are formed over one insulating surface; and
wherein the floating gate electrode comprises a plurality of particles.
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Abstract
The present invention provides a semiconductor device capable of being mass-produced and a manufacturing method of the semiconductor device. The present invention also provides a semiconductor device using an extreme thin integrated circuit and a manufacturing method of the semiconductor device. Further, the present invention provides a low power consumption semiconductor device and a manufacturing method of the semiconductor device. According to one aspect of the present invention, a semiconductor device that has a semiconductor nonvolatile memory element transistor over an insulating surface in which a floating gate electrode of the memory transistor is formed by a plurality of conductive particles or semiconductor particles is provided.
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Citations
76 Claims
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1. A semiconductor device comprising:
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a first transistor comprising;
a first semiconductor region;
a first insulating film formed over the first semiconductor region;
a floating gate electrode formed over the first insulating film;
a second insulating film formed over the floating gate electrode, and a first gate electrode formed over the second insulating film; and
a second transistor comprising;
a second semiconductor region;
a third insulating film formed over the second semiconductor region; and
a second gate electrode formed over the third insulating film;
wherein the first transistor and the second transistor are formed over one insulating surface; and
wherein the floating gate electrode comprises a plurality of particles. - View Dependent Claims (13, 17, 21, 25, 29, 33, 37, 43, 47, 51, 55, 73)
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2. A semiconductor device comprising:
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a first transistor comprising;
a first semiconductor region;
a first insulating film formed over the first semiconductor region;
a floating gate electrode formed over the first insulating film;
a second insulating film formed over the floating gate electrode; and
a first gate electrode formed over the second insulating film;
a second transistor comprising;
a second semiconductor region;
a third insulating film formed over the second semiconductor region; and
a second gate electrode formed over the third insulating film; and
a third transistor comprising;
a third semiconductor region;
a fourth insulating film formed over the third semiconductor region; and
a third gate electrode formed over the fourth insulating film;
wherein the second semiconductor region has source and drain regions doped with an impurity element imparting one of n-type and p-type conductivity, wherein the third semiconductor region comprises;
source and drain regions doped with an impurity element imparting the one of n-type and p-type conductivity; and
a region that is covered by the third gate electrode and that is doped with an impurity element imparting the other of n-type and p-type conductivity, wherein the first to third transistors are formed over one insulating surface, and wherein the floating gate electrode comprises a plurality of particles. - View Dependent Claims (3, 14, 18, 22, 26, 30, 34, 38, 41, 44, 48, 52, 56, 74)
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4. A semiconductor device comprising:
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a first transistor comprising;
a first semiconductor region;
a first insulating film formed over the first semiconductor region;
a floating gate electrode formed over the first insulating film;
a second insulating film formed over the floating gate electrode; and
a first gate electrode formed over the second insulating film;
a thin film integrated circuit comprising a second transistor comprising;
a second semiconductor region;
a third insulating film formed over the second semiconductor region; and
a second gate electrode formed over the third insulating film; and
an antenna;
wherein the first transistor and the second transistor are formed over one insulating surface, and wherein the first floating gate electrode comprises a plurality of particles. - View Dependent Claims (7, 9, 11, 15, 19, 23, 27, 31, 35, 39, 45, 49, 53, 57, 75)
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5. A semiconductor device comprising:
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a first transistor comprising;
a first semiconductor region;
a first insulating film formed over the first semiconductor region;
a floating gate electrode formed over the first insulating film;
a second insulating film formed over the floating gate electrode; and
a first gate electrode formed over the second insulating film;
a second transistor comprising;
a second semiconductor region;
a third insulating film formed over the second semiconductor region; and
a second gate electrode formed over the third insulating film;
a thin film integrated circuit having a third transistor comprising;
a third semiconductor region;
a fourth insulating film formed over the third semiconductor region; and
a third gate electrode formed over the fourth insulating film; and
an antenna;
wherein the first to third transistors are formed over one insulating surface, wherein the first floating gate electrode comprises a plurality of particles;
wherein the second semiconductor region has source and drain regions doped with an impurity element imparting one of n-type and p-type conductivity, and wherein the third semiconductor region has source and drain regions doped with an impurity element imparting the one of n-type and p-type conductivity and a region that is covered by the third gate electrode and that is doped with an impurity element imparting the other of n-type and p-type conductivity. - View Dependent Claims (6, 8, 10, 12, 16, 20, 24, 28, 32, 36, 40, 42, 46, 50, 54, 58, 68, 69, 70, 76)
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59. A method for manufacturing a semiconductor device comprising the steps of:
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forming a semiconductor film over an insulating surface;
forming a crystalline semiconductor film by improving crystallinity of the semiconductor film;
forming first and second semiconductor regions by removing a part of the crystalline semiconductor film by etching;
forming a first insulating film over the first and second semiconductor regions;
forming a plurality of particles over the first insulating film;
removing a part of the plurality of particles over the second semiconductor region by etching;
forming a second insulating film over the first insulating film and the plurality of particles that is remained after the step of removing the part of the plurality of particles;
forming a first conductive film over the second insulating film;
forming first and second gate electrodes by removing a part of the first conductive layer by etching;
forming first source and drain regions and second source and drain regions in the first and second semiconductor regions respectively by doping an impurity element to the first and second semiconductor regions; and
forming a first source wiring in contact with the first source region, a first drain wiring in contact with the first drain region, a second source wiring in contact with the second source region and a second drain wiring in contact with the second drain region. - View Dependent Claims (62, 65)
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60. A method for manufacturing a semiconductor device comprising the steps of:
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forming a semiconductor film over an insulating surface;
forming a crystalline semiconductor film by improving crystallinity of the semiconductor film;
forming first and second semiconductor regions by removing a part of the crystalline semiconductor film by etching;
forming a first insulating film over the first and second semiconductor regions;
forming a plurality of particles over the first insulating film;
removing a part of the plurality of particles formed over the second semiconductor region by etching;
forming a second insulating film over the first insulating film and the plurality of particles that is remained after the step of removing the part of the plurality of particles;
forming a first conductive film over the second insulating film;
forming a first gate electrode, a second gate electrode, and a floating gate electrode by removing a part of the first conductive layer and the plurality of particles that is remained;
forming first source and drain regions and second source and drain regions in the first and second semiconductor regions respectively by doping an impurity element to the first and second semiconductor regions; and
forming a first source wiring in contact with the first source region, a first drain wiring in contact with the first drain region, a second source wiring in contact with the second source region and a second drain wiring in contact with the second drain region. - View Dependent Claims (63, 66)
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61. A method for manufacturing a semiconductor device comprising the steps of:
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forming a semiconductor film over a substrate;
forming a crystalline semiconductor film by improving crystallinity of the semiconductor film;
forming first to third semiconductor regions by removing a part of the crystalline semiconductor film by etching;
forming a first insulating film over the first to third semiconductor regions;
forming a plurality of particles over the first insulating film;
removing a part of the plurality of particles formed over the second and third semiconductor regions by etching;
forming a second insulating film over the first insulating film and the plurality of particles which are remained after the step of removing the part of the plurality of particles;
forming a first conductive film over the second insulating film;
forming first to third gate electrodes by removing a part of the first conductive film by etching;
covering the first and second semiconductor regions by masks;
doping an impurity element imparting one of n-type and p-type conductivity to the third semiconductor region at an angle of from 0 to 60 degrees to a surface of the third semiconductor region and along one direction to the third gate electrode;
removing the masks;
doping an impurity element imparting the other of n-type and p-type conductivity to the first to third semiconductor regions at a vertical angle;
forming first source and drain regions in the first semiconductor region, second source and drain regions in the second semiconductor region, and third source and drain regions in the third semiconductor region by heating; and
forming a first source wiring in contact with the first source region, a first drain wiring in contact with the first drain region, a second source wiring in contact with the second source region, a second drain wiring in contact with the second drain region, a third source wiring in contact with the third source region, and a third drain wiring in contact with the third drain region. - View Dependent Claims (64, 67, 71, 72)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsIsobe, Atsuo, Yamaguchi, Tetsuji, Godo, Hiromichi, Yamazaki, Shunpei
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current257/72
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CPC Class CodesH01L 2029/7863 with an LDD consisting of m...H01L 2224/32225 the item being non-metallic...H01L 2224/48091 ArchedH01L 2224/48227 connecting the wire to a bo...H01L 2224/48465 the other connecting portio...H01L 2224/73265 Layer and wire connectorsH01L 2224/83385 Shape, e.g. interlocking fe...H01L 24/32 of an individual layer conn...H01L 24/73 Means for bonding being of ...H01L 27/1214 comprising a plurality of T...H01L 27/127 with a particular formation...H01L 27/13 combined with thin-film or ...H01L 29/78621 with LDD structure or an ex...H01L 29/78624 the source and the drain re...H01L 29/78627 with a significant overlap ...H01L 2924/00 Indexing scheme for arrange...H01L 2924/00012 Relevant to the scope of th...H01L 2924/00014 the subject-matter covered ...H01L 2924/01005 Boron [B]H01L 2924/01006 Carbon [C]View All
