Liquid crystal display device and fabricating method thereof

• US 20050263768A1
• Filed: 05/26/2005
• Published: 12/01/2005
• Est. Priority Date: 05/27/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Ahn, Byung Chul
• Granted Patent: US 7,468,527 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A thin film transistor substrate and a fabricating method simplify a process and enlarge a capacitance value of a storage capacitor without any reduction of aperture ratio. A transparent first conductive layer and an opaque second conductive layer of a double-layer structured gate line are formed having a step coverage. A pixel electrode is provided on the gate insulating film within a pixel hole of said pixel area passing through the passivation film to be connected to the thin film transistor. A storage capacitor overlaps with the pixel electrode with having the gate insulating film therebetween and has a lower storage electrode protruded from the first conductive layer.

Claims

1. A liquid crystal display device, comprising:

a double-layer structure of a gate line, the double layer having a first transparent conductive layer and a second opaque conductive layer and having a step coverage;

a data line crossing to the gate line to define a pixel region;

a gate insulating film between the gate line and the data line;

a thin film transistor connected to the gate line and the data line;

a semiconductor layer defining a channel of the thin film transistor and overlapping with the data line;

a passivation film covering the data line and the thin film transistor;

a pixel electrode on the gate insulating film within a pixel hole of the pixel region passing through the passivation film; and

a storage capacitor overlapping with the pixel electrode having the gate insulating film therebetween and having a lower storage electrode extended from the first transparent conductive layer.

2. The device as claimed in claim 1, further comprising:

a gate pad including a lower gate pad electrode having the double-layer structure connected to the gate line, and an upper gate pad electrode within a contact hole passing through the gate insulating film and the passivation film.

3. The device as claimed in claim 1, further comprising:

a data pad including a lower data pad electrode connected to the data line, and an upper data pad electrode within a contact hole passing through the passivation film,

wherein the semiconductor layer overlaps with the lower data pad electrode.

4. The device as claimed in claim 1, wherein the pixel electrode is substantially laterally connected to the drain electrode through the pixel hole.

5. The device substrate as claimed in claim 3, wherein the upper data pad electrode is substantially laterally connected to the lower data pad electrode through the contact hole.

6. The device as claimed in claim 1, wherein the gate electrode is connected to the gate line.

7. A method of fabricating a liquid crystal display device, comprising:

forming a gate line and a gate electrode having a double-layer structure with a transparent conductive layer and a gate pattern including a lower storage electrode having the transparent conductive layer on a substrate using a first mask;

forming a gate insulating film covering the gate pattern, and forming a semiconductor layer and a source/drain layer on the gate insulating film using a second mask; and

forming a passivation film having a pixel hole and forming a pixel electrode connected to the drain electrode and overlapping with the lower storage electrode on the gate insulating film within the pixel hole using a third mask.

8. The method as claimed in claim 7, wherein the first mask includes a first half-tone mask.

9. The method as claimed in claim 7, wherein the second mask includes a diffractive exposure mask.

10. The method as claimed in claim 8, wherein the third mask includes a second half-tone mask.

11. The method as claimed in claim 7, wherein the forming a gate line and a gate electrode includes:

forming a first conductive layer as the transparent conductive layer and a second conductive layer on the substrate;

forming first and second photo-resist patterns having a different thickness on the second conductive layer by a photolithography using the first mask;

forming the gate line, the gate electrode and the lower storage electrode by patterning the first and second conductive layers using an etching through the first and second photo-resist patterns;

removing the second conductive layer on the lower storage electrode by an etching using the first photo-resist pattern; and

removing the first photo-resist pattern.

12. The method as claimed in claim 11, wherein the second conductive layer remains on the lower storage electrode using the etching.

13. The method as claimed in claim 11, further comprising thinning the first photo-resist pattern and removing the second photo-resist pattern using an ashing after forming the gate line, the gate electrode and the lower storage electrode.

14. The method as claimed in claim 7, wherein the data line overlaps with the semiconductor layer.

15. The method as claimed in claim 7, wherein the lower storage electrode is protruded from the first conductive layer of the gate line.

16. The method as claimed in claim 7, wherein the forming a gate line and a gate electrode further includes forming a lower gate pad electrode connected to the gate line;

and

wherein forming a passivation film further includes forming a contact hole passing through the passivation film and the gate insulating film by exposing the lower gate pad electrode and forming an upper gate pad electrode connected to the lower gate pad electrode within the contact hole.

17. The method as claimed in claim 16, wherein the lower gate pad electrode includes the double-layer.

18. The method as claimed in claim 16, wherein forming a gate insulating film further includes forming the lower data pad electrode connected to the data line, and

forming a passivation film further includes forming a second contact hole passing through the passivation film and the upper data pad electrode connected to the lower data pad electrode within the second contact hole.

19. The method as claimed in claim 18, wherein forming a passivation film includes:

forming a passivation film on the source and drain electrodes;

forming first and second photo-resist patterns having a different thickness on the passivation film by a photolithography using the second mask;

forming the first contact hole by an etching using the first and second photo-resist patterns;

forming the pixel hole and the second contact hole by the etching using the first photo-resist pattern;

forming a transparent conductive layer on the first photo-resist pattern; and

forming a transparent conductive pattern having the pixel electrode, the upper gate pad electrode and the upper data pad electrode by removing the first photo-resist pattern and the transparent conductive layer using a lift-off.

20. The method as claimed in claim 19, further comprising thinning the first photo-resist pattern by an ashing and removing the second photo-resist pattern after forming the first contact hole.

21. The method as claimed in claim 19, wherein the forming the pixel hole and the second contact hole includes forming an exposed portion of the drain electrode and the lower data pad electrode.

22. The method as claimed in claim 21, wherein the pixel electrode is substantially laterally connected to the drain electrode.

23. The method as claimed in claim 21, wherein the upper data pad electrode is substantially laterally connected to the lower data pad electrode.

24. The method as claimed in claim 21, wherein the forming the pixel hole and the second contact hole includes etching a semiconductor layer under the exposed portion of the drain electrode and the lower data pad electrode.

25. The method as claimed in claim 21, wherein the forming the pixel hole and the second contact hole includes over-etching the passivation film such that the edge of the first photo-resist pattern is more protruded than the edge of the passivation film.

26. The method as claimed in claim 7, wherein the first and second conductive layers have constant step coverage.