Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress
First Claim
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1. A method, comprising:
- forming a first dielectric layer over a first transistor element and a second transistor element, said first dielectric layer having a first specified intrinsic mechanical stress;
forming a mask layer above said first and second transistor elements to expose a first portion of said first dielectric layer formed above said first transistor element and cover a second portion of said first dielectric layer formed above said second transistor element; and
modifying said first intrinsic stress in said first portion to a modified intrinsic stress by ion bombardment of said first portion.
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Abstract
By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.
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Citations
30 Claims
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1. A method, comprising:
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forming a first dielectric layer over a first transistor element and a second transistor element, said first dielectric layer having a first specified intrinsic mechanical stress;
forming a mask layer above said first and second transistor elements to expose a first portion of said first dielectric layer formed above said first transistor element and cover a second portion of said first dielectric layer formed above said second transistor element; and
modifying said first intrinsic stress in said first portion to a modified intrinsic stress by ion bombardment of said first portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method, comprising:
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forming a first dielectric layer over a first transistor element and a second transistor element, said first dielectric layer having a first specified intrinsic mechanical stress;
selectively removing a first portion of said first dielectric layer over said first transistor element;
forming a second dielectric layer over said first transistor element and a second portion of said first dielectric layer formed above said second transistor element, said second dielectric layer having a second intrinsic stress differing from said first intrinsic stress; and
selectively removing a second portion of said second dielectric layer formed above said second portion of said first dielectric layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A semiconductor device, comprising:
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a first transistor element having a first channel region and a first dielectric layer enclosing said first transistor element, said first dielectric layer inducing a first stress in said first channel region; and
a second transistor element having a second channel region and a second dielectric layer, said second dielectric layer enclosing said second transistor element, said second dielectric layer inducing a second stress in said second channel region, the second stress differing from said first stress. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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Specification