Technique for creating different mechanical stress in different channel regions by forming an etch stop layer having differently modified intrinsic stress

• US 20050263825A1
• Filed: 02/15/2005
• Published: 12/01/2005
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Frohberg, Kai, Schaller, Matthias, Aminpur, Massud
• Granted Patent: US 7,517,816 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

By providing a contact etch stop layer, the stress in channel regions of different transistor types may be effectively controlled, wherein tensile and compressive stress portions of the contact etch stop layer may be obtained by well-established processes, such as wet chemical etch, plasma etch, ion implantation, plasma treatment and the like. Hence, a significant improvement in transistor performance may be obtained while not significantly contributing to process complexity.

Claims

1. A method, comprising:

forming a first dielectric layer over a first transistor element and a second transistor element, said first dielectric layer having a first specified intrinsic mechanical stress;

forming a mask layer above said first and second transistor elements to expose a first portion of said first dielectric layer formed above said first transistor element and cover a second portion of said first dielectric layer formed above said second transistor element; and

modifying said first intrinsic stress in said first portion to a modified intrinsic stress by ion bombardment of said first portion.

2. The method of claim 1, further comprising removing said mask layer and forming a second dielectric layer having a second intrinsic stress above said dielectric layer, said second intrinsic stress being different than said first intrinsic stress.

3. The method of claim 2, further comprising selectively removing material of said second dielectric layer over said second portion.

4. The method of claim 2, further comprising forming a second mask layer to cover a first portion of said second dielectric layer formed above said first portion of said first dielectric layer, and to expose a second portion of said second dielectric layer formed above said second portion of said first dielectric layer.

5. The method of claim 4, further comprising modifying said second intrinsic stress in said second portion of said second dielectric layer by an ion bombardment to create a second modified intrinsic stress in said second portion of said second dielectric layer.

6. The method of claim 1, further comprising selectively forming a second dielectric layer having a second intrinsic stress over said first transistor element prior to forming said first dielectric layer.

7. The method of claim 6, wherein selectively forming said second dielectric layer comprises forming said second dielectric layer above said first and second transistor elements, forming a second mask layer covering said first transistor element and exposing said second transistor element and removing a first portion of said second dielectric layer exposed by said second mask layer.

8. The method of claim 7, wherein forming said second dielectric layer above said first and second transistor elements comprises depositing a first liner, depositing a stress-inducing layer substantially determining said second intrinsic stress and depositing a second liner, said first and second liners being selectively etchable with respect to said stress-inducing layer.

9. The method of claim 8, wherein removing said first portion of said second dielectric layer comprises selectively etching said second liner to expose said stress-inducing layer and selectively removing an exposed portion of said stress-inducing layer to expose said first liner.

10. The method of claim 9, further comprising removing said second mask layer, forming a third mask layer to cover said second transistor element and expose said first transistor element, and selectively etching said second liner to expose said stress-inducing layer over said first transistor element.

11. A method, comprising:

forming a first dielectric layer over a first transistor element and a second transistor element, said first dielectric layer having a first specified intrinsic mechanical stress;

selectively removing a first portion of said first dielectric layer over said first transistor element;

forming a second dielectric layer over said first transistor element and a second portion of said first dielectric layer formed above said second transistor element, said second dielectric layer having a second intrinsic stress differing from said first intrinsic stress; and

selectively removing a second portion of said second dielectric layer formed above said second portion of said first dielectric layer.

12. The method of claim 11, wherein forming said first dielectric layer comprises depositing a first liner, depositing a stress-inducing layer and depositing a second liner, said first and second liners being selectively etchable with respect to said stress-inducing layer.

13. The method of claim 12, further comprising selectively etching said second liner over said first transistor element while covering said second transistor with a resist mask.

14. The method of claim 13, further comprising removing said resist mask and selectively etching said stress-inducing layer over said first transistor element while using said second liner over said second transistor element as an etch mask.

15. The method of claim 14, wherein forming said second dielectric layer comprises forming said second dielectric layer over said first transistor element and over said second transistor element, forming a resist mask to cover said first transistor element and to expose said second transistor element and etching said second dielectric layer to remove at least a portion of said second dielectric layer over said second transistor element.

16. The method of claim 15, wherein said etching is performed as a dry etching process.

17. The method of claim 13, wherein selectively etching said second liner is performed as a wet etching process.

18. The method of claim 14, wherein said stress-inducing layer is etched with a wet etch process.

19. The method of claim 11, wherein forming said first dielectric layer comprises forming a stress-inducing layer above said first and second transistor elements and forming a liner on said stress-inducing layer, said liner differing from said stress-inducing layer in material composition.

20. The method of claim 19, wherein selectively removing said first portion comprises forming a resist mask to cover said second transistor element and to expose said first transistor element, and etching said liner and said stress-inducing layer by a dry etch process.

21. The method of claim 20, wherein forming said second dielectric layer comprises depositing said second dielectric layer above said first transistor element and said second transistor element, forming a resist mask to cover said first transistor element and to expose said second transistor element, and dry etching said second dielectric layer while using said liner for controlling said dry etch process.

22. A semiconductor device, comprising:

a first transistor element having a first channel region and a first dielectric layer enclosing said first transistor element, said first dielectric layer inducing a first stress in said first channel region; and

a second transistor element having a second channel region and a second dielectric layer, said second dielectric layer enclosing said second transistor element, said second dielectric layer inducing a second stress in said second channel region, the second stress differing from said first stress.

23. The semiconductor device of claim 22, wherein said first dielectric layer has a first thickness and said second dielectric layer has a second thickness other than said first thickness.

24. The semiconductor device of claim 22, further comprising an interlayer dielectric formed above said first and second dielectric layers, a minimum thickness of said interlayer dielectric being greater than said first thickness and said second thickness.

25. The semiconductor device of claim 22, wherein said first and second transistor elements form a complementary transistor pair.

26. The semiconductor device of claim 22, wherein said first transistor element is a P-type transistor and said first induced stress is a compressive stress.

27. The semiconductor device of claim 26, wherein said second transistor element is an N-type transistor and said second induced stress is a tensile stress.

28. The semiconductor device of claim 22, wherein at least one of said first and second dielectric layers comprises a liner and a stress-inducing layer, said liner being located between said stress-inducing layer and a gate electrode structure and drain and source terminals of at least one of said first and second transistor elements.

29. The semiconductor device of claim 22, wherein said first channel region and said second channel region have substantially the same configuration except for a conductivity type.

30. The semiconductor device of claim 22, wherein a gate length of said first and second transistor elements is less than approximately 50 nm.