Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge

• US 20050263833A1
• Filed: 08/03/2005
• Published: 12/01/2005
• Est. Priority Date: 12/06/2002
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Sengoku, Naohisa, Matsumoto, Michikazu
• Application Number:
  US11/195,624
• Publication Number:
  US 20050263833A1
• Time in Patent Office: Days
• US Class Current: 257/405
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.

Claims

1. An apparatus for evaluating an amount of charge, the apparatus comprising:

a substrate having a substantially intrinsic undoped silicon layer;

p-type regions dotted as discrete islands in the undoped silicon layer; and

a first insulating layer provided over the undoped silicon layer and the p-type regions.

2. The apparatus of claim 1, wherein a second insulating layer is provided in a region of the substrate located below the undoped silicon layer.

3. The apparatus of claim 2, wherein the second insulating layer has a thickness not less than 1 nm and not more than 500 nm.

4. The apparatus of claim 1, wherein the undoped silicon layer has a thickness not less than 10 nm and not more than 10 μ

m.

5. The apparatus of claim 1, wherein a concentration of an impurity contained in the p-type regions is not less than 1×

10¹⁶ cm<sup>−

3</sup> and not more than 1×

10²³ cm<sup>−

3</sup>.

6. The apparatus of claim 1, wherein a concentration of an impurity contained in the undoped silicon layer is not more than 1×

10¹⁵ cm<sup>−

3</sup>.

7. The apparatus of claim 1, wherein the first insulating film has a thickness not less than 1 nm and not more than 500 nm.

8. The apparatus of claim 1, further comprising:

a third insulating layer composed of an insulating material and provided on a back surface of the semiconductor substrate.

9. The apparatus of claim 8, wherein the third insulating layer has a thickness not less than 1 nm and not more than 500 nm.

10. The apparatus of claim 1, further comprising:

a conductor film on the first insulating layer.

11-20. -20. (canceled)