Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology

• US 20050263834A1
• Filed: 07/07/2005
• Published: 12/01/2005
• Est. Priority Date: 10/23/2003
• Status: Abandoned Application

• Current Assignee: Antonio L.P. Rotondaro, Karen H. Kirmse, Yuanning Chen
• Original Assignee: Antonio L.P. Rotondaro, Karen H. Kirmse, Yuanning Chen
• Inventors: Rotondaro, Antonio L. P., Chen, Yuanning, Kirmse, Karen H.
• Application Number:
  US11/177,142
• Publication Number:
  US 20050263834A1
• Time in Patent Office: Days
• US Class Current: 257/408
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.

Claims

1-14. -14. (canceled)

15. A transistor comprising:

a gate structure formed over a substrate;

sidewall spacers formed on the substrate adjacent the gate structure, the sidewall spacers including a low dielectric constant material encapsulated by one or more nitride materials; and

source/drain regions formed within the substrate adjacent the gate structure, the sidewall spacers serving to guide dopants implanted into the substrate to form the source/drain regions into desired locations within the substrate.

16. The transistor of claim 15, wherein at least one of the low dielectric constant material and the encapsulating nitride materials have a thickness of between about 50 to about 500 Angstroms.

17. The transistor of claim 15, wherein the low dielectric constant material has a dielectric constant of less than about 3.5.

18. The transistor of claim 15, wherein the low dielectric constant material includes at least one of black diamond from Applied Materials Inc., coral from Novellus Systems, Inc. and one or more low-k materials manufactured by the JSR Microelectronics Corporation.

19. The transistor of claim 15, further comprising:

a capping oxide layer formed over the gate structure, but under the sidewall spacers and encapsulating nitride materials, wherein an etching process utilized to pattern the capping oxide layer is selective relative to the nitride materials such that the sidewall spacers are substantially unaffected by an etchant utilized in the process, the sidewall spacers thus substantially retaining their respective shapes and remaining effective to guide dopants into desired locations within the substrate.

20. The transistor of claim 19, wherein the capping oxide layer mitigates loss of implanted dopants from the substrate up into overlying materials.

21-22. -22. (canceled)