Structure of dummy pattern in semiconductor device

• US 20050263904A1
• Filed: 05/19/2005
• Published: 12/01/2005
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated (SK Hynix Inc.)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Lee, Se Young
• Granted Patent: US 7,105,927 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed herein in a dummy pattern structure of a semiconductor device. According to the present invention, the dummy pattern structure comprises daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlayer insulating film where metal wirings are formed, thus being arranged in the whole region while constituting a polygon shape, and mother dummy patterns respectively formed at places corresponding to the middles of the polygon, which is formed by the daughter dummy patterns. Generation of metal residues in a region where metal wirings are not formed when the metal wirings are formed by means of a damascene process are prevented. Also, a delamination phenomenon that interlayer insulating films are fallen apart can be prevented.

Claims

1. A dummy pattern structure of a semiconductor device, comprising:

daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlayer insulating film where metal wirings are formed, thus being arranged in the whole region while constituting a polygon shape.

2. The dummy pattern structure as claimed in claim 1, further comprising mother dummy patterns respectively formed at places corresponding to the middles of the polygon, which is formed by the daughter dummy patterns.

3. The dummy pattern structure as claimed in claim 2, wherein the daughter dummy patterns and the mother dummy patterns are formed by the same process as a process of forming a metal wiring.

4. The dummy pattern structure as claimed in claim 2, wherein the daughter dummy patterns, the mother dummy patterns and the metal wiring are formed by means of a damascene process.

5. The dummy pattern structure as claimed in claim 1, wherein the daughter dummy patterns are arranged in the form of one of a triangle, a square, a pentagon, a hexagon and an octagon.

6. The dummy pattern structure as claimed in claim 1, wherein the daughter dummy patterns are arranged in the form of one of a triangle, a square, a pentagon, a hexagon and an octagon.

7. The dummy pattern structure as claimed in claim 1, wherein a distance between the daughter dummy patterns is 3 to 100 μ

m.

8. The dummy pattern structure as claimed in claim 2, wherein a distance between the daughter dummy pattern and the mother dummy pattern is 3 to 100 μ

m.

9. The dummy pattern structure as claimed in claim 2, wherein each of the daughter dummy patterns and the mother dummy patterns is formed in a variety of polygonal shapes, wherein the daughter dummy patterns and the mother dummy patterns are formed in the same polygon among the variety of the polygonal shapes, or have a shape in which the variety of the polygons are mixed.

10. The dummy pattern structure as claimed in claim 9, wherein in each of the daughter dummy patterns and the mother dummy patterns, the length of one side of the polygon is 3 to 100 μ

m.

11. The dummy pattern structure as claimed in claim 9, wherein an area of each of the daughter dummy patterns and the mother dummy patterns is 9 to 10000 μ

m².

12. The dummy pattern structure as claimed in claim 9, wherein the daughter dummy patterns and the mother dummy patterns have the polygon of the same area, the mother dummy patterns have an area wider than that of the daughter dummy pattern, or the daughter dummy patterns have an area wider than that of the mother dummy pattern.

13. The dummy pattern structure as claimed in claim 2, wherein the mother dummy patterns and the daughter dummy patterns are formed to have the density of 10 to 50% of the entire region where the mother dummy patterns and the daughter dummy patterns are formed.

14. The dummy pattern structure as claimed in claim 2, wherein the mother dummy patterns and the daughter dummy patterns are formed to have the same density as the density of the metal wiring in the region where the metal wiring is formed, or the density 15% higher than the density of the metal wiring in the region where the metal wiring is formed.

15. The dummy pattern structure as claimed in claim 2, wherein an area of the region where the mother dummy patterns and the daughter dummy patterns are formed is 250000 μ

m² or less.

16. The dummy pattern structure as claimed in claim 15, wherein if the area of a region where the mother dummy patterns and the daughter dummy patterns are formed is 250000 μ

m² or more, pad patterns of an area wider than that of the dummy patterns are further formed.

17. The dummy pattern structure as claimed in claim 16, wherein the pad patterns are formed to have the density of 10 to 40%.