Efficient pulse amplitude modulation transmit modulation

• US 20050264333A1
• Filed: 08/02/2005
• Published: 12/01/2005
• Est. Priority Date: 05/23/2001
• Status: Active Grant

• Current Assignee: Dirk Leipold, Kenneth J. Maggio, Robert B. Staszewski
• Original Assignee: Dirk Leipold, Kenneth J. Maggio, Robert B. Staszewski
• Inventors: Leipold, Dirk, Staszewski, Robert B., Maggio, Kenneth J.
• Granted Patent: US 7,667,511 B2
• Time in Patent Office: Days
• US Class Current: 327/172
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 7/02 Amplitude modulation, i.e. PAM
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04B 2001/0491 with frequency synthesizers, frequency converters or modulators

Abstract

Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

Claims

1-29. -29. (canceled)

30. A pulse amplitude modulator, comprising:

a power amplifier having an input port for receiving an oscillator clock signal and a plurality of digitally controlled parallel connected transistors that provide for amplitude modulation.

40. A pulse amplitude modulator as defined in claim 30, further comprising a matching network, the matching network coupled to said digitally controlled parallel connected transistors.

42. A pulse amplitude modulator as defined in claim 30, further comprising AND gates.

43. A pulse amplitude modulator as defined in claim 30, wherein the amplitude modulation is responsive to a selected number of said active parallel connected transistors.

44. A pulse modulator as defined in claim 30, further comprising means for controlling the number of said parallel connected transistors that are active in accordance with the digital control signal.

31. A pulse amplitude modulator, comprising:

a power amplifier having an input port for receiving an input signal and a plurality of digitally controlled parallel connected transistors that provide for amplitude modulation.

32. A digitally controlled oscillator (DCO) having an input and a tuning word adjustment circuit coupled to the input, the tuning word adjustment circuit being responsive to an amplitude control signal.

33. The digitally controlled oscillator (DCO) as defined in claim 32, wherein an output signal from said digitally controlled oscillator is useable as a clock signal.

34. A transmitter circuit, comprising:

a pulse amplitude modulator (PAM) including;

an oscillator for providing a clock signal; and

a digitally controlled power amplifier responsive to the clock signal, the power amplifier including a plurality of digitally controlled elements that provide for amplitude modulation.

35. The transmitter circuit as defined in claim 34, wherein the plurality of digitally controlled elements comprises a plurality of parallel connected transistors.

41. A transmitter circuit as defined in claim 34, further comprising a matching network, the matching network coupled to said digitally controlled elements.

36. A transmitter circuit, comprising:

a digitally controlled power amplifier responsive to an input signal, the power amplifier including a plurality of digitally controlled elements that provide for amplitude modulation, wherein the plurality of digitally controlled elements comprise a plurality of parallel connected transistors.

37. A transmitter circuit, comprising:

a pulse amplitude modulator (PAM) including;

a digitally controlled oscillator (DCO) having an input and further comprising a tuning word adjustment circuit coupled to the input of the DCO, the tuning word adjustment circuit being responsive to an amplitude control signal,

the DCO providing a clock signal; and

a digitally controlled power amplifier responsive to the DCO clock signal and the amplitude control signal.

38. A transmitter circuit as defined in claim 37, wherein the tuning word adjustment circuit changes the DCO frequency for a single clock cycle, whereby the phase and amplitude controls are orthogonal.

39. A transmitter circuit as defined in claim 37, wherein the amplitude control signal performs amplitude modulation.

45. A power amplifier, comprising:

a plurality of digitally controlled parallel connected transistors wherein the number of active parallel connected transistors determines the power amplifier output amplitude.